AD9761 datasheet(13/23 Pages) AD

13 / 23 page

AD9761

–13–

REV. A

The positive output compliance range is slightly dependent on

the full-scale output current, IOUTFS. It degrades slightly from

its nominal 1.25 V for an IOUTFS = 10 mA to 1.00 V for an

IOUTFS = 2 mA. Applications requiring the AD9761’s output

(i.e., VOUTA and/or VOUTB) to extend to its output compliance

range should size RLOAD accordingly. Operation beyond this

compliance range will adversely affect the AD9761’s linearity

performance and subsequently degrade its distortion perfor-

mance. Note, the optimum distortion performance of the

AD9761 is obtained by restricting its output(s) as seen at

IOUT(A/B) and QOUT(A/B) to within

±0.5 V.

DIGITAL INPUTS AND INTERLEAVED INTERFACE

CONSIDERATIONS

The AD9761 digital interface consists of 10 data input pins, a

clock input pin, and three control pins. It is designed to support

a clock rate up to 40 MSPS. The 10-bit parallel data inputs

follow standard positive binary coding, where DB9 is the most

significant bit (MSB) and DB0 is the least significant bit (LSB).

IOUTA (or QOUTA) produces a full-scale output current when

all data bits are at Logic 1. IOUTB (or QOUTB) produces a

complementary output, with the full-scale current split between

the two outputs as a function of the input code.

STATE

MACHINE

"I" AND "Q" DATA

CLOCK

SELECT

RESET/SLEEP

WRITE

"Q" DATA

CLOCK

"I" DATA

"I"

INPUT

"I"

FILTER

"Q"

INPUT

"Q"

INPUT

Figure 28. Block Diagram of Digital Interface

The AD9761 interfaces with a single 10-bit digital input bus

that supports interleaved I and Q input data. Figure 28 shows a

simplified block diagram of the digital interface circuitry consist-

ing of two banks of edge triggered registers, two multiplexers,

and a state machine. Interleaved I and Q input data is presented

at the DATA input bus, where it is then latched into the se-

lected I or Q input register on the rising edge of the WRITE

input. The output of these input registers is transferred in pairs

to their respective interpolator filters’ register after each Q write

on the rising edge of the CLOCK input (refer to Timing Dia-

gram in Figure 2). A state machine ensures the proper pairing of

I and Q input data to the interpolation filter’s inputs.

The SELECT signal at the time of the rising edge of the WRITE

signal determines which input register latches the input data. If

SELECT is high around the rising edge of WRITE the data is

latched into the I register of the AD9761. If SELECT is low

around the rising edge of the WRITE, the data is latched into

the Q register of the AD9761. If SELECT is kept in one state

while data is repeatedly writing to the AD9761, the data will be

written into the selected filter register at half the input data rate

since the data is always assumed to be interleaved.

The state machine controls the generation of the divided clock

and hence pairing of I and Q data inputs. After the AD9761 is

reset, the state machine keeps track of the paired I and Q data.

The state transition diagram is shown in Figure 29, in which all

the states are defined. A transition in state occurs upon the

rising edge of CLOCK and is a function of the current state as

well as status of SELECT, WRITE and SLEEP. The state ma-

chine is reset on the first rising CLOCK edge while RESET

remains high. Upon RESET returning low, a state transition will

occur on the first rising edge of CLOCK. The most recent I and Q

data samples are transferred to the correct interpolation filter

only upon entering state FILTER DATA.

Note, it is possible to ensure proper pairing of I and Q

data inputs without issuing RESET high. This may be

accomplished by writing two or more successive Q data

inputs followed by a clock. In this case, the state machine

will advance to either the RESET or FILTER DATA state.

The state machine will advance to the ONE-I state upon

writing I data followed by a clock.

ONE, I

RESET

FILTER

DATA

I or Q or N

I = WRITE & SELECT FOLLOWED BY A CLOCK

Q = WRITE &

SELECT FOLLOWED BY A CLOCK

N = CLOCK ONLY, NO WRITE

Q or N

Figure 29. State Transition Diagram of AD9761 Digital

Interface

An example helps illustrate the digital timing and control re-

quirements to ensure proper pairing of I and Q data. In this

example, the AD9761 is assumed to interface with a host pro-

cessor on a dedicated data bus and the state machine is reset by

asserting a Logic Level “1” to the RESET/SLEEP input for a

duration of one clock cycle. In the timing diagram shown in

Figure 30, WRITE and CLOCK are tied together while SELECT

is updated at the same instance as DATA. Since SELECT is

high upon RESET returning low, I data is latched into the I

input register on the first rising WRITE. On the next rising

WRITE edge, the Q data is latched into its input register and

the outputs of both input registers are latched into their respec-

tive I and Q filter registers. The sequence of events is repeated

on the next rising WRITE edge with the new I data being

latched into the I input register.

The digital inputs are CMOS compatible with logic thresholds,

VTHRESHOLD set to approximately half the digital positive supply

(DVDD) or VTHRESHOLD = DVDD/2 (

±20%).

The internal digital circuitry of the AD9761 is capable of oper-

ating over a digital supply range of 2.7 V to 5.5 V. As a result,

the digital inputs can also accommodate TTL levels when DVDD

is set to accommodate the maximum high level voltage, VOH(MAX),

of the TTL drivers. A DVDD of 3 V to 3.3 V will typically

AD9761 Datasheet(PDF) 13 Page - Analog Devices

AD9761 Datasheet(HTML) 13 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23

Datasheet Download

Link URL