TMS320DM8147 datasheet(2/370 Pages) TI1

2 / 370 page

TMS320DM8148, TMS320DM8147, TMS320DM8146

SPRS647D – MARCH 2011 – REVISED SEPTEMBER 2012

www.ti.com

•

One 16/24/30-bit and one 16/24-bit Output

• Six Configurable UART/IrDA/CIR Modules

– Composite or S-Video Analog Output

– UART0 With Modem Control Signals

– MacroVision® Support Available

– Supports up to 3.6864 Mbps UART0/1/2

– Digital HDMI 1.3 transmitter With Integrated

– Supports up to 12 Mbps UART3/4/5

PHY

– SIR, MIR, FIR (4.0 MBAUD), and CIR

– Advanced Video Processing Features Such

• Four Serial Peripheral Interfaces (SPIs) [up to

as Scan/Format/Rate Conversion

48-MHz]

– Three Graphics Layers and Compositors

– Each With Four Chip-Selects

• Dual 32-bit DDR2/DDR3 SDRAM Interfaces

• Three MMC/SD/SDIO Serial Interfaces [up to 48-

– Supports up to DDR2-800 and DDR3-800

MHz]

– Up to Eight x 8 Devices Total 2 GB Total

– Three Supporting up to 1-/4-/8-Bit Modes

Address Space

• Dual Controller Area Network (DCAN) Modules

– Dynamic Memory Manager (DMM)

– CAN Version 2 Part A, B

•

Programmable Multi-Zone Memory

• Four Inter-Integrated Circuit (I2C Bus™) Ports

Mapping and Interleaving

• Six Multi-Channel Audio Serial Ports (McASP)

•

Enables Efficient 2D Block Accesses

– Dual Ten Serializer Transmit/Receive Ports

•

Supports Tiled Objects in 0°, 90°, 180°, or

– Quad Four Serializer Transmit/Receive Ports

270° Orientation and Mirroring

– DIT-Capable For S/PDIF (All Ports)

•

Optimizes Interlaced Accesses

• Multi-Channel Buffered Serial Port (McBSP)

• General Purpose Memory Controller (GPMC)

– Transmit/Receive Clocks up to 48 MHz

– 8-/16-bit Multiplexed Address/Data Bus

– Two Clock Zones and Two Serial Data Pins

– 512M-Byte Total Address Space Divided

– Supports TDM, I2S, and Similar Formats

Among up to 8 Chip Selects

• Serial ATA (SATA) 3.0 Gbps Controller With

– Glueless Interface to NOR Flash, NAND

Integrated PHY

Flash (BCH/Hamming Error Code Detection),

– Direct Interface to One Hard Disk Drive

SRAM and Pseudo-SRAM

– Hardware-Assisted Native Command

– Error Locator Module (ELM) Outside of

Queuing (NCQ) from up to 32 Entries

GPMC to Provide Upto 16-Bit/512-Bytes

– Supports Port Multiplier and Command-

Hardware ECC for NAND

Based Switching

– Flexible Asynchronous Protocol Control for

• Real-Time Clock (RTC)

Interface to FPGA, CPLD, ASICs, and so

– One-Time or Periodic Interrupt Generation

Forth

• Up to 128 General-Purpose I/O (GPIO) Pins

• Enhanced Direct-Memory-Access (EDMA)

Controller

• One Spin Lock Module with up to 128 Hardware

Semaphores

– Four Transfer Controllers

• One Mailbox Module with 12 Mailboxes

– 64/8 Independent DMA/QDMA Channels

• On-Chip ARM ROM Bootloader (RBL)

• Dual Port Ethernet (10/100/1000 Mb/s) With

Optional Switch

• Power, Reset, and Clock Management

– IEEE 802.3 Compliant (3.3V I/O Only)

– Multiple Independent Core Power Domains

– MII/RMII/GMII/RGMII Media Independent I/Fs

– Multiple Independent Core Voltage Domains

– Management Data I/O (MDIO) Module

– Support for Three Operating Points

(OPP166/120/100) per Voltage Domain

– Reset Isolation

– Clock Enable/Disable Control for

– IEEE-1588 Time-Stamping and Industrial

Subsystems and Peripherals

Ethernet Protocols

• 32KB Embedded Trace Buffer™ (ETB™) and 5-

• Dual USB 2.0 Ports With Integrated PHYs

pin Trace Interface for Debug

– USB2.0 High-/Full-Speed Clients

• IEEE-1149.1 (JTAG) Compatible

– USB2.0 High-/Full-/Low-Speed Hosts, or OTG

• 684-Pin Pb-Free BGA Package (CYE Suffix),

– Supports End Points 0-15

0.8-mm Ball Pitch With Via Channel™

• One PCI Express 2.0 Port With Integrated PHY

Technology to Reduce PCB Cost

– Single Port With 1 Lane at 5.0 GT/s

• 45-nm CMOS Technology

– Configurable as Root Complex or Endpoint

• 1.8-/3.3-V Dual Voltage Buffers for General I/O

• Eight 32-bit General-Purpose Timers (Timer1–8)

• One System Watchdog Timer (WDT 0)

High-Performance System-on-Chip (SoC)

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