TMS320DM8147 datasheet(7/370 Pages) TI1

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TMS320DM8148, TMS320DM8147, TMS320DM8146

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SPRS647D – MARCH 2011 – REVISED SEPTEMBER 2012

Revision History

NOTE: Page numbers for previous revisions may differ from page numbers in the current version.

This data manual revision history highlights the technical changes made to the SPRS647C device-specific

data manual to make it an SPRS647D revision.

Scope: Applicable updates to the DM814x DaVinci™ Video DMP device family, specifically relating to the

TMS320DM8148/47/46 devices, which are now in the production data (PD) stage of development have

been incorporated.

•

OPP50 is not supported

•

SmartReflex (AVS) is not supported

•

Deep Sleep Mode is not supported

•

HDMI HDCP encryption is not supported

•

LPDDR mode is no longer supported

•

OPP 166% (CYE1) (1.35 V) SR3.0 devices support a DSP frequency of 750 MHz

SEE

ADDITIONS/MODIFICATIONS/DELETIONS

OPP50 is not supported

SmartReflex (AVS) is not supported

Deep Sleep Mode is not supported

Updated/Changed the "TBD" chapter references to the device-specific TRM.

Updated/Changed the "Microprocessors" and "MPUs" title references to "Processors" or "Core" where

applicable.

Global

Updated/Changed "Digital Media Processors: to "Video Processors"

HDMI HDCP encryption is not supported

Deleted LPDDR mode; no longer supported

Added updates for Global Authoring for Translation (for example, no Latin abbreviations like e.g. or i.e.)

Updated/Changed the product status from "Product Preview (PP)" to "Production Data (PD)" stage of

development.

SGX530 3D Graphics Engine:

•

Updated/Changed the subbullet "Delivers up to ... from "18" to "25" MPoly/sec

Section 1.1

Features

•

Deleted "SmartReflex™ Technology (Level 2b)" subbullet

•

Deleted "/50" from the "Support for Three Operating Points ..." bullet

Table 2-2, Characteristics of the Processor:

Section 2.2

Device Characteristics

•

Added "ARM® Cortex™-A8, Main ID Register Variant/Revision, r3p2" row

Section 2.4

Section 2.4.3, ARM Cortex-A8 Interrupt Controller (AINTC):

ARM® Cortex™-A8

Microprocessor Unit

•

Added a note that the AINTC for General-Purpose devices does not support the generation of FIQs

(MPU) Subsystem

to the ARM. [Cleared E2E Issue]

Overview

Section 3.2.6, EMAC [(R)(G)MII Modes] and MDIO:

Table 3-7, EMAC[0] Terminal Functions [(R)(G)MII]:

•

Updated/Changed lead-in "TBD" for each EMAC mode (that is, (G)MII, RMI, and RGMII) to "An

EMAC bootmode must be selected via the BTMODE[4:0] ..." paragraph

•

Updated/Changed the EMAC[0]_GMTCLK DESCRIPTION from "Asynchronous" to "Synchronous"

[Cleared LitBug #SDOCM00088607]

Section 3.2

Terminal Functions

Table 3-8,EMAC[1] Terminal Functions [(R)(G)MII]:

•

Updated/Changed lead-in "TBD" for each EMAC mode (that is, (G)MII, RMI, and RGMII) to "An

EMAC bootmode must be selected via the BTMODE[4:0] ..." paragraph

•

Updated/Changed the EMAC[1]_GMTCLK DESCRIPTION from "Asynchronous" to "Synchronous"

[Cleared LitBug #SDOCM00088607]

Contents

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