TC7109CLW datasheet(20/32 Pages) MICROCHIP

20 / 32 page

TC7109/A

DS21456D-page 20

 2002-2012 Microchip Technology Inc.

4.2

Handshake Mode

The Handshake mode provides an interface to a wide

variety of external devices. The byte enables may be

used as byte identification flags, or as load enables,

and external latches may be clocked by the rising edge

of CE/LOAD. A handshake interface to Intel® micropro-

cessors using an 8255 PPI is shown in Figure . The

handshake operation with the 8255 is controlled by

inverting its Input Buffer Full (IBF) flag to drive the

SEND input to the TC7109A, and using the CE/LOAD

to drive the 8255 strobe. The internal control register of

the PPI should be set in MODE 1 for the port used. If

the 8255 IBF flag is LOW and the TC7109A is in Hand-

shake mode, the next word will be strobed into the port.

The strobe will cause IBF to go HIGH (SEND goes

LOW), which will keep the enabled byte outputs active.

The PPI will generate an interrupt which, when

executed, will result in the data being read. The IBF will

be reset LOW when the byte is read, causing the

TC7109A to sequence into the next byte. The MODE

input to the TC7109A is connected to the control line on

the PPI.

The data from every conversion will be sequenced in

two bytes in the system, if this output is left HIGH, or

tied HIGH separately. (The data access must take less

time than a conversion.) The output sequence can be

obtained on demand if this output is made to go from

LOW to HIGH and the interrupt may be used to reset

the MODE bit.

Conversions may be obtained on command under soft-

ware control by driving the RUN/HOLD input to the

TC7109A by a bit of the 8255. Another peripheral

device may be serviced by the unused port of the 8255.

The Handshake mode is particularly useful for directly

interfacing to industry standard UARTs (such as Intersil

HD-6402), providing a means of serially transmitting

converted data with minimum component count.

A typical UART connection is shown in Figure . In this

circuit, any word received by the UART causes the

UART DR (Data Ready) output to go HIGH. The MODE

input to the TC7109A goes HIGH, triggering the

TC7109A into Handshake mode. The high order byte is

output to the UART and when the UART has trans-

ferred the data to the Transmitter register, TBRE

(SEND) goes HIGH again, LBEN will go HIGH, driving

the UART DRR (Data Ready Reset), which will signal

the end of the transfer of data from the TC7109A to the

UART.

An extension of the typical connection to several

TC7109A’s with one UART is shown in Figure 4-7. In

this circuit, the word received by the UART (available at

the RBR outputs when DR is HIGH) is used to select

which converter will handshake with the UART. Up to

eight TC7109A’s may interface with one UART, with no

external components. Up to 256 converters may be

accessed

one

serial

line

with

additional

components.

FIGURE 4-6:

TC7109 Typical UART Interface

GND

BUFF OSC OUT

STATUS

HBEN

B1 - B8

TEST

LBEN

MODE

CE/LOAD

SEND

V+

TC7109A

CLK

RESET

5–12

GND

RRD

RBR1–8

SFD

RR1

TRO

TRC

RRC

EPE

CLS1

CLS2

SBS

CRL

*TBR1–8

TRE

DRR

TBRL

TBRE

HD-640R

CMOS UART

+5V

GND

+5V

GND

Serial

Input

Serial

Output

GND

+5V

GND

+5V

-5V

+5V or Open

GND

3.58MHz

Crystal

Analog GND

External

Reference

–

Input

CAZ

0.33

μF

CINT

0.15

μF

0.01

μF

3–8

9–16

B9 - B12,

POL, OR

26–33

For lowest power consumption, TBR1-TBR8 inputs should have 100k

Ω pull-up resistors to +5V.

Send any word to UART to transmit latest result.

RINT 20kΩ

100k

0.2VREF

1VREF

CD4060B

REF IN-

REF CAP-

REF CAP+

REF IN+

IN HI

IN LO

COM

INT

REF OUT

BUFF

V-

RUN/HOLD

OSC SEL

OSC OUT

OSC IN

–

*Note:

TC7109CLW Datasheet(PDF) 20 Page - Microchip Technology

TC7109CLW Datasheet(HTML) 20 Page - Microchip Technology

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32

Datasheet Download

Link URL