LAN9500AI datasheet(17/66 Pages) SMSC

17 / 66 page

USB 2.0 to 10/100 Ethernet Controller

Datasheet

SMSC LAN950x Family

Revision 1.1 (04-18-13)

DATASHEET

Note 3.2

Configuration strap values are latched on power-on reset and system reset. Configuration

straps are identified by an underlined symbol name. Signals that function as configuration

straps must be augmented with an external resistor when connected to a load.

EEPROM

Chip Select

EECS

This pin drives the chip select output of the

external EEPROM.

Note:

The EECS output may tri-state briefly

during power-up. Some EEPROM

devices may be prone to false selection

during this time. When an EEPROM is

used, an external pull-down resistor is

recommended on this signal to prevent

false selection. Refer to your EEPROM

manufacturer’s datasheet for additional

information.

EEPROM

Clock

EECLK

(PD)

This pin drives the EEPROM clock of the external

EEPROM.

Power Select

Configuration

Strap

PWR_SEL

(PD)

Determines the default power setting when no

EEPROM is present.

0 = The device is bus powered.

1 = The device is self powered.

See Note 3.2 for more information on

configuration straps.

Table 3.3 JTAG Pins

NUM PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

JTAG Test

Port Reset

(Internal PHY

Mode)

nTRST

(PU)

In internal PHY mode, this active-low pin

functions as the JTAG test port reset input.

Receive Data

(External

PHY Mode)

RXD0

(PD)

In external PHY mode, this pin functions as the

receive data 0 input from the external PHY.

JTAG Test

Data Out

(Internal PHY

Mode)

TDO

In internal PHY mode, this pin functions as the

JTAG data output.

PHY Reset

(External

PHY Mode)

nPHY_RST

In external PHY mode, this active-low pin

functions as the PHY reset output.

Table 3.2 EEPROM Pins (continued)

NUM PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

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