LAN9500AI datasheet(18/66 Pages) SMSC

18 / 66 page

USB 2.0 to 10/100 Ethernet Controller

Datasheet

Revision 1.1 (04-18-13)

SMSC LAN950x Family

DATASHEET

JTAG Test

Clock

(Internal PHY

Mode)

TCK

(PU)

In internal PHY mode, this pin functions as the

JTAG test clock. The maximum operating

frequency of this clock is 25MHz.

Receive Data

(External

PHY Mode)

RXD1

(PD)

In external PHY mode, this pin functions as the

receive data 1 input from the external PHY.

JTAG Test

Mode Select

(Internal PHY

Mode)

TMS

(PU)

In internal PHY mode, this pin functions as the

JTAG test mode select.

Receive Data

(External

PHY Mode)

RXD2

(PD)

In external PHY mode, this pin functions as the

receive data 2 input from the external PHY.

JTAG Test

Data Input

(Internal PHY

Mode)

TDI

(PU)

In internal PHY mode, this pin functions as the

JTAG data input.

Receive Data

(External

PHY Mode)

RXD3

(PD)

In external PHY mode, this pin functions as the

receive data 3 input from the external PHY.

Table 3.4 Miscellaneous Pins

NUM PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

PHY Select

PHY_SEL

(PD)

Selects whether to use the internal Ethernet PHY

or the external PHY connected to the MII port.

0 = Internal PHY is used.

1 = External PHY is used.

System Reset

nRESET

(PU)

This active-low pin allows external hardware to

reset the device.

Note:

(LAN9500A/LAN9500Ai only)

This pin may be used to signal

PME_CLEAR when PME mode of

operation is in effect. Refer to

Chapter 6, "PME Operation," on

page 41 for additional information.

Table 3.3 JTAG Pins (continued)

NUM PINS

NAME

SYMBOL

BUFFER

TYPE

DESCRIPTION

LAN9500AI Datasheet(PDF) 18 Page - SMSC Corporation

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