STM32F303VCT6 datasheet(110/132 Pages) STMICROELECTRONICS

110 / 132 page

Electrical characteristics

STM32F302xx/STM32F303xx

110/132

DocID023353 Rev 6

Figure 33. Typical connection diagram using the ADC

1. Refer to Table 66 for the values of RAIN.

2. Cparasitic represents the capacitance of the PCB (dependent on soldering and PCB layout quality) plus the

pad capacitance (roughly 7 pF). A high Cparasitic value will downgrade conversion accuracy. To remedy

this, fADC should be reduced.

General PCB design guidelines

Power supply decoupling should be performed as shown in Figure 11. The 10 nF capacitor

should be ceramic (good quality) and it should be placed as close as possible to the chip.

6.3.19

DAC electrical specifications

VDD

AINx

IL±1 μA

0.6 V

RAIN(1)

Cparasitic

VAIN

0.6 V

12-bit

converter

Sample and hold ADC

converter

Table 70. DAC characteristics

Symbol

Parameter

Min

Typ

Max

Unit

Comments

VDDA

Analog supply voltage for

DAC ON

2.4

3.6

RLOAD(1) Resistive load with buffer ON

VREF+

Positive reference voltage

2.4

3.6

VREF+ must be always equal to or

less than VDDA

RO(1)

Impedance output with buffer

OFF

When the buffer is OFF, the Minimum

resistive load between DAC_OUT

and VSS to have a 1% accuracy is

1.5 M

CLOAD(1) Capacitive load

Maximum capacitive load at

DAC_OUT pin (when the buffer is

ON).

DAC_OUT

min(1)

Lower DAC_OUT voltage

with buffer ON

0.2

It gives the maximum output

excursion of the DAC.

It corresponds to 12-bit input code

(0x0E0) to (0xF1C) at VREF+ = 3.6 V

and (0x155) and (0xEAB) at VREF+ =

2.4 V

DAC_OUT

max(1)

Higher DAC_OUT voltage

with buffer ON

VDDA – 0.2

DAC_OUT

min(1)

Lower DAC_OUT voltage

with buffer OFF

-0.5

It gives the maximum output

excursion of the DAC.

DAC_OUT

max(1)

Higher DAC_OUT voltage

with buffer OFF

VREF+ – 1LSB V

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