PI7C8140AMAE datasheet(39/82 Pages) PERICOM

39 / 82 page

PI7C8140A

2-PORT PCI-TO-PCI BRIDGE

Page 39 of 82

March 20, 2007 – Revision 1.01

Delayed read completion transactions, comprised of all memory read, I/O read, & configuration

read transactions.

Delayed read completion transactions complete on the target bus, and the read data is queued in the read

data buffers. A delayed read completion transaction proceeds in the direction opposite that of the

original delayed read request; that is, a delayed read completion transaction proceeds from the target

bus to the initiator bus.

The bridge does not combine or merge write transactions:

The bridge does not combine separate write transactions into a single write transaction—this

optimization is best implemented in the originating master.

The bridge does not merge bytes on separate masked write transactions to the same DWORD

address—this optimization is also best implemented in the originating master.

The bridge does not collapse sequential write transactions to the same address into a single write

transaction—the PCI Local Bus Specification does not permit this combining of transactions.

4.2

GENERAL ORDERING GUIDELINES

Independent transactions on primary and secondary buses have a relationship only when those

transactions cross the bridge.

The following general ordering guidelines govern transactions crossing the bridge:

The ordering relationship of a transaction with respect to other transactions is determined when the

transaction completes, that is, when a transaction ends with a termination other than target retry.

Requests terminated with target retry can be accepted and completed in any order with respect to

other transactions that have been terminated with target retry. If the order of completion of delayed

requests is important, the initiator should not start a second delayed transaction until the first one

has been completed. If more than one delayed transaction is initiated, the initiator should repeat all

delayed transaction requests, using some fairness algorithm. Repeating a delayed transaction cannot

be contingent on completion of another delayed transaction. Otherwise, a deadlock can occur.

Write transactions flowing in one direction have no ordering requirements with respect to write

transactions flowing in the other direction. The bridge can accept posted write transactions on both

interfaces at the same time, as well as initiate posted write transactions on both interfaces at the

same time.

The acceptance of a posted memory write transaction as a target can never be contingent on the

completion of a non-locked, non-posted transaction as a master. This is true for the bridge and must

also be true for other bus agents. Otherwise, a deadlock can occur.

The bridge accepts posted write transactions, regardless of the state of completion of any delayed

transactions being forwarded across the bridge.

4.3

ORDERING RULES

Table 4-1 shows the ordering relationships of all the transactions and refers by number to the ordering

rules that follow.

07-0067

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