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MPC875CVR133 Datasheet(PDF) 45 Page - Freescale Semiconductor, Inc |
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MPC875CVR133 Datasheet(HTML) 45 Page - Freescale Semiconductor, Inc |
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45 / 84 page  MPC875/MPC870 PowerQUICC™ Hardware Specifications, Rev. 4 Freescale Semiconductor 45 IEEE 1149.1 Electrical Specifications 12 IEEE 1149.1 Electrical Specifications Table 16 provides the JTAG timings for the MPC875/MPC870 shown in Figure 37 through Figure 40. Figure 37. JTAG Test Clock Input Timing Table 16. JTAG Timing Num Characteristic All Frequencies Unit Min Max J82 TCK cycle time 100.00 — ns J83 TCK clock pulse width measured at 1.5 V 40.00 — ns J84 TCK rise and fall times 0.00 10.00 ns J85 TMS, TDI data setup time 5.00 — ns J86 TMS, TDI data hold time 25.00 — ns J87 TCK low to TDO data valid — 27.00 ns J88 TCK low to TDO data invalid 0.00 — ns J89 TCK low to TDO high impedance — 20.00 ns J90 TRST assert time 100.00 — ns J91 TRST setup time to TCK low 40.00 — ns J92 TCK falling edge to output valid — 50.00 ns J93 TCK falling edge to output valid out of high impedance — 50.00 ns J94 TCK falling edge to output high impedance — 50.00 ns J95 Boundary scan input valid to TCK rising edge 50.00 — ns J96 TCK rising edge to boundary scan input invalid 50.00 — ns TCK J82 J83 J82 J83 J84 J84 |
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