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M68ICS08GR Datasheet(PDF) 222 Page - Freescale Semiconductor, Inc |
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M68ICS08GR Datasheet(HTML) 222 Page - Freescale Semiconductor, Inc |
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222 / 408 page ![]() Input/Output Ports (I/O) Technical Data MC68HC908GR8 — Rev 4.0 222 Input/Output Ports (I/O) MOTOROLA 16.6.2 Data Direction Register D Data direction register D (DDRD) determines whether each port D pin is an input or an output. Writing a logic 1 to a DDRD bit enables the output buffer for the corresponding port D pin; a logic 0 disables the output buffer. DDRD6–DDRD0 — Data Direction Register D Bits These read/write bits control port D data direction. Reset clears DDRD6–DDRD0, configuring all port D pins as inputs. 1 = Corresponding port D pin configured as output 0 = Corresponding port D pin configured as input NOTE: Avoid glitches on port D pins by writing to the port D data register before changing data direction register D bits from 0 to 1. Figure 16-15 shows the port D I/O logic. Address: $0007 Bit 7 654321 Bit 0 Read: 0 DDRD6 DDRD5 DDRD4 DDRD3 DDRD2 DDRD1 DDRD0 Write: Reset: 00000000 Figure 16-14. Data Direction Register D (DDRD) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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