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M68ICS08GR Datasheet(PDF) 224 Page - Freescale Semiconductor, Inc |
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M68ICS08GR Datasheet(HTML) 224 Page - Freescale Semiconductor, Inc |
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224 / 408 page ![]() Input/Output Ports (I/O) Technical Data MC68HC908GR8 — Rev 4.0 224 Input/Output Ports (I/O) MOTOROLA 16.6.3 Port D Input Pullup Enable Register The port D input pullup enable register (PTDPUE) contains a software configurable pullup device for each of the seven port D pins. Each bit is individually configurable and requires that the data direction register, DDRD, bit be configured as an input. Each pullup is automatically and dynamically disabled when a port bit’s DDRD is configured for output mode. PTDPUE6–PTDPUE0 — Port D Input Pullup Enable Bits These writeable bits are software programmable to enable pullup devices on an input port bit. 1 = Corresponding port D pin configured to have internal pullup 0 = Corresponding port D pin has internal pullup disconnected Address: $000F Bit 7 6 543 21 Bit 0 Read: 0 PTDPUE6 PTDPUE5 PTDPUE4 PTDPUE3 PTDPUE2 PTDPUE1 PTDPUE0 Write: Reset: 00 000 000 Figure 16-16. Port D Input Pullup Enable Register (PTDPUE) Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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