M68ICS08GR datasheet(240/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

Technical Data

MC68HC908GR8 — Rev 4.0

240

Serial Communications Interface (SCI)

MOTOROLA

18.5.2.5 Inversion of Transmitted Output

The transmit inversion bit (TXINV) in SCI control register 1 (SCC1)

reverses the polarity of transmitted data. All transmitted values, including

idle, break, start, and stop bits, are inverted when TXINV is at logic 1.

See SCI Control Register 1.

18.5.2.6 Transmitter Interrupts

These conditions can generate CPU interrupt requests from the SCI

transmitter:

•

SCI transmitter empty (SCTE) — The SCTE bit in SCS1 indicates

that the SCDR has transferred a character to the transmit shift

Setting the SCI transmit interrupt enable bit, SCTIE, in SCC2

enables the SCTE bit to generate transmitter CPU interrupt

requests.

•

Transmission complete (TC) — The TC bit in SCS1 indicates that

the transmit shift register and the SCDR are empty and that no

break or idle character has been generated. The transmission

complete interrupt enable bit, TCIE, in SCC2 enables the TC bit to

generate transmitter CPU interrupt requests.

18.5.3 Receiver

Figure 18-5 shows the structure of the SCI receiver.

18.5.3.1 Character Length

The receiver can accommodate either 8-bit or 9-bit data. The state of the

M bit in SCI control register 1 (SCC1) determines character length.

When receiving 9-bit data, bit R8 in SCI control register 2 (SCC2) is the

ninth bit (bit 8). When receiving 8-bit data, bit R8 is a copy of the eighth

bit (bit 7).

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