M68ICS08GR datasheet(243/408 Pages) FREESCALE

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Serial Communications Interface (SCI)

Functional Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Serial Communications Interface (SCI)

243

18.5.3.3 Data Sampling

The receiver samples the PE1/RxD pin at the RT clock rate. The RT

clock is an internal signal with a frequency 16 times the baud rate. To

adjust for baud rate mismatch, the RT clock is resynchronized at the

following times (see Figure 18-6):

•

After every start bit

•

After the receiver detects a data bit change from logic 1 to logic 0

(after the majority of data bit samples at RT8, RT9, and RT10

returns a valid logic 1 and the majority of the next RT8, RT9, and

RT10 samples returns a valid logic 0)

To locate the start bit, data recovery logic does an asynchronous search

for a logic 0 preceded by three logic 1s. When the falling edge of a

possible start bit occurs, the RT clock begins to count to 16.

Figure 18-6. Receiver Data Sampling

To verify the start bit and to detect noise, data recovery logic takes

samples at RT3, RT5, and RT7. Table 18-2 summarizes the results of

the start bit verification samples.

RT CLOCK

RESET

START BIT

QUALIFICATION

START BIT

VERIFICATION

DATA

SAMPLING

SAMPLES

CLOCK

RT CLOCK

STATE

START BIT

LSB

PE1/RxD

Freescale Semiconductor, Inc.

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