M68ICS08GR datasheet(277/408 Pages) FREESCALE

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System Integration Module (SIM)

Reset and System Initialization

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

System Integration Module (SIM)

277

An internal reset clears the SIM counter (see SIM Counter), but an

external reset does not. Each of the resets sets a corresponding bit in

the SIM reset status register (SRSR). See SIM Registers.

19.4.1 External Pin Reset

The RST pin circuit includes an internal pullup device. Pulling the

asynchronous RST pin low halts all processing. The PIN bit of the SIM

reset status register (SRSR) is set as long as RST is held low for a

minimum of 67 CGMXCLK cycles, assuming that neither the POR nor

the LVI was the source of the reset. See Table 19-2 for details. Figure

19-4 shows the relative timing.

Figure 19-4. External Reset Timing

19.4.2 Active Resets from Internal Sources

All internal reset sources actively pull the RST pin low for 32 CGMXCLK

cycles to allow resetting of external peripherals. The internal reset signal

IRST continues to be asserted for an additional 32 cycles. See Figure

19-5. An internal reset can be caused by an illegal address, illegal

opcode, COP timeout, LVI, or POR. See Figure 19-6.

NOTE:

For LVI or POR resets, the SIM cycles through 4096 CGMXCLK cycles

during which the SIM forces the RST pin low. The internal reset signal

Table 19-2. PIN Bit Set Timing

Reset Type

Number of Cycles Required to Set PIN

POR/LVI

4163 (4096 + 64 + 3)

All others

67 (64 + 3)

RST

IAB

VECT H VECT L

CGMOUT

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