M68ICS08GR datasheet(280/408 Pages) FREESCALE

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System Integration Module (SIM)

Technical Data

MC68HC908GR8 — Rev 4.0

280

System Integration Module (SIM)

MOTOROLA

The COP module is disabled if the RST pin or the IRQ pin is held at Vtst

while the MCU is in monitor mode. The COP module can be disabled

only through combinational logic conditioned with the high voltage signal

on the RST or the IRQ pin. This prevents the COP from becoming

disabled as a result of external noise. During a break state, Vtst on the

RST pin disables the COP module.

19.4.2.3 Illegal Opcode Reset

The SIM decodes signals from the CPU to detect illegal instructions. An

illegal instruction sets the ILOP bit in the SIM reset status register

(SRSR) and causes a reset.

If the stop enable bit, STOP, in the mask option register is logic 0, the

SIM treats the STOP instruction as an illegal opcode and causes an

illegal opcode reset. The SIM actively pulls down the RST pin for all

internal reset sources.

19.4.2.4 Illegal Address Reset

An opcode fetch from an unmapped address generates an illegal

address reset. The SIM verifies that the CPU is fetching an opcode prior

to asserting the ILAD bit in the SIM reset status register (SRSR) and

resetting the MCU. A data fetch from an unmapped address does not

generate a reset. The SIM actively pulls down the RST pin for all internal

reset sources.

19.4.2.5 Low-Voltage Inhibit (LVI) Reset

The low-voltage inhibit module (LVI) asserts its output to the SIM when

the VDD voltage falls to the LVITRIPF voltage. The LVI bit in the SIM reset

status register (SRSR) is set, and the external reset pin (RST) is held low

while the SIM counter counts out 4096 CGMXCLK cycles. Sixty-four

CGMXCLK cycles later, the CPU is released from reset to allow the reset

vector sequence to occur. The SIM actively pulls down the RST pin for

all internal reset sources.

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M68ICS08GR Datasheet(PDF) 280 Page - Freescale Semiconductor, Inc