M68ICS08GR datasheet(332/408 Pages) FREESCALE

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Timebase Module (TBM)

Technical Data

MC68HC908GR8 — Rev 4.0

332

Timebase Module (TBM)

MOTOROLA

NOTE:

Do not change TBR2–TBR0 bits while the timebase is enabled

(TBON = 1).

TACK— Timebase ACKnowledge

The TACK bit is a write-only bit and always reads as 0. Writing a logic

1 to this bit clears TBIF, the timebase interrupt flag bit. Writing a logic

0 to this bit has no effect.

1 = Clear timebase interrupt flag

0 = No effect

TBIE — Timebase Interrupt Enabled

This read/write bit enables the timebase interrupt when the TBIF bit

becomes set. Reset clears the TBIE bit.

1 = Timebase interrupt enabled

0 = Timebase interrupt disabled

TBON — Timebase Enabled

This read/write bit enables the timebase. Timebase may be turned off

to reduce power consumption when its function is not necessary. The

counter can be initialized by clearing and then setting this bit. Reset

clears the TBON bit.

1 = Timebase enabled

0 = Timebase disabled and the counter initialized to 0s

21.6 Interrupts

The timebase module can interrupt the CPU on a regular basis with a

rate defined by TBR2:TBR0. When the timebase counter chain rolls

over, the TBIF flag is set. If the TBIE bit is set, enabling the timebase

interrupt, the counter chain overflow will generate a CPU interrupt

request.

Interrupts must be acknowledged by writing a logic 1 to the TACK bit.

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M68ICS08GR Datasheet(PDF) 332 Page - Freescale Semiconductor, Inc