M68ICS08GR datasheet(345/408 Pages) FREESCALE

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Timer Interface Module (TIM)

Functional Description

MC68HC908GR8 — Rev 4.0

Technical Data

MOTOROLA

Timer Interface Module (TIM)

345

22.5.8 Buffered PWM Signal Generation

Channels 0 and 1 can be linked to form a buffered PWM channel whose

output appears on the TCH0 pin. The TIM channel registers of the linked

pair alternately control the pulse width of the output.

Setting the MS0B bit in TIM channel 0 status and control register (TSC0)

links channel 0 and channel 1. The TIM channel 0 registers initially

control the pulse width on the TCH0 pin. Writing to the TIM channel 1

registers enables the TIM channel 1 registers to synchronously control

the pulse width at the beginning of the next PWM period. At each

subsequent overflow, the TIM channel registers (0 or 1) that control the

pulse width are the ones written to last. TSC0 controls and monitors the

buffered PWM function, and TIM channel 1 status and control register

(TSC1) is unused. While the MS0B bit is set, the channel 1 pin, TCH1,

is available as a general-purpose I/O pin.

NOTE:

In buffered PWM signal generation, do not write new pulse width values

to the currently active channel registers. User software should track the

currently active channel to prevent writing a new value to the active

channel. Writing to the active channel registers is the same as

generating unbuffered PWM signals.

22.5.9 PWM Initialization

To ensure correct operation when generating unbuffered or buffered

PWM signals, use the following initialization procedure:

1. In the TIM status and control register (TSC):

a. Stop the TIM counter by setting the TIM stop bit, TSTOP.

b. Reset the TIM counter and prescaler by setting the TIM reset

bit, TRST.

2. In the TIM counter modulo registers (TMODH:TMODL), write the

value for the required PWM period.

3. In the TIM channel x registers (TCHxH:TCHxL), write the value for

the required pulse width.

4. In TIM channel x status and control register (TSCx):

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