M68ICS08GR datasheet(346/408 Pages) FREESCALE

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Timer Interface Module (TIM)

Technical Data

MC68HC908GR8 — Rev 4.0

346

Timer Interface Module (TIM)

MOTOROLA

a. Write 0:1 (for unbuffered output compare or PWM signals) or

1:0 (for buffered output compare or PWM signals) to the

mode select bits, MSxB:MSxA. See Table 22-3.

b. Write 1 to the toggle-on-overflow bit, TOVx.

c. Write 1:0 (to clear output on compare) or 1:1 (to set output on

compare) to the edge/level select bits, ELSxB:ELSxA. The

output action on compare must force the output to the

complement of the pulse width level. (See Table 22-3.)

NOTE:

In PWM signal generation, do not program the PWM channel to toggle

on output compare. Toggling on output compare prevents reliable 0%

duty cycle generation and removes the ability of the channel to self-

correct in the event of software error or noise. Toggling on output

compare can also cause incorrect PWM signal generation when

changing the PWM pulse width to a new, much larger value.

5. In the TIM status control register (TSC), clear the TIM stop bit,

TSTOP.

Setting MS0B links channels 0 and 1 and configures them for buffered

PWM operation. The TIM channel 0 registers (TCH0H:TCH0L) initially

control the buffered PWM output. TIM status control register 0 (TSCR0)

controls and monitors the PWM signal from the linked channels.

Clearing the toggle-on-overflow bit, TOVx, inhibits output toggles on TIM

overflows. Subsequent output compares try to force the output to a state

it is already in and have no effect. The result is a 0% duty cycle output.

Setting the channel x maximum duty cycle bit (CHxMAX) and setting the

TOVx bit generates a 100% duty cycle output. (See TIM Channel Status

and Control Registers.)

22.6 Interrupts

The following TIM sources can generate interrupt requests:

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M68ICS08GR Datasheet(PDF) 346 Page - Freescale Semiconductor, Inc