Z84C9012VSC00TR datasheet(13/56 Pages) ZILOG

13 / 56 page

PS011804-0612

Block Descriptions

Z84C90 KIO Serial/Parallel Counter/Timer

Product Specification

In the default state of the KIO, each serial channel supports full duplex communication

with separate transmit and receive data lines, two modem control signals (CTS and DCD)

and separate transmit and receive clock inputs. Optionally, additional modem and CPU/

DMA control signals can be obtained through the PIA port.

For more information about the operation of this portion of the logic, please refer to the

Z8420/Z84C20 PIO Product Specification (PS0180).

Figure 5. SIO Block Diagram

Data

Control

Serial

Channel

Interrupt

Control

Lines

Data

Clocks

Sync

Wait/Ready

Modem or

Other

Control

Modem or

Other

Control

Serial

Channel

Data

Clocks

Sync

Wait/Ready

Channel A

Control

and

Status

Registers

Internal

Control

Logic

CPU

Bus

I/O

Interrupt

Control

Logic

Channel B

Control

and

Status

Registers

Channel A

Channel B

Channel A

Control

and

Status

Channel B

Control

and

Status

Z84C9012VSC00TR Datasheet(PDF) 13 Page - Zilog, Inc.

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