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ICS9LPRS436CKILF Datasheet(PDF) 15 Page - Integrated Device Technology

Part # ICS9LPRS436CKILF
Description  Low Power Clock for Intel Atom짰-Based Systems
PDF  20 Pages
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Manufacturer  IDT [Integrated Device Technology]
Direct Link  http://www.idt.com
Logo IDT - Integrated Device Technology

ICS9LPRS436CKILF Datasheet(HTML) 15 Page - Integrated Device Technology

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IDT®
Low Power Clock for Intel Atom®-Based Systems
1561A — 06/01/10
ICS9LPRS436C
Low Power Clock for Intel Atom
®-Based Systems
15
SMBus Table: Byte Count Register
Byte 8
Name
Control Function
Type
0
1
PWD
Bit 7
Reserved
0
Bit 6
Reserved
0
Bit 5
Reserved
0
Bit 4
BC4
RW
0
Bit 3
BC3
RW
1
Bit 2
BC2
RW
1
Bit 1
BC1
RW
1
Bit 0
BC0
RW
1
SMBus Table: Watch Dog Timer Control Register
Byte 9
Name
Control Function
Type
0
1
PWD
Bit 7
HWD_EN
Watchdog Hard Alarm Enable
RW
Disable
Enable
0
Bit 6
WD Hard Status
WD Hard Alarm Status
R
Normal
Alarm
X
Bit 5
WDTCtrl
Watch Dog Alarm Time base
Control
R0
Bit 4
HWD3
WD Hard Alarm Timer Bit 3
RW
1
Bit 3
HWD2
WD Hard Alarm Timer Bit 2
RW
1
Bit 2
HWD1
WD Hard Alarm Timer Bit 1
RW
1
Bit 1
HWD0
WD Hard Alarm Timer Bit 0
RW
1
Bit 0
Reserved
Reserved
RW
-
-
0
SMBus Table: Skew programming Register
Byte 10
Name
Control Function
Type
0
1
PWD
Bit 7
CPUSkw3
RW
0
Bit 6
CPUSkw2
RW
0
Bit 5
CPUSkw1
RW
0
Bit 4
CPUSkw0
RW
0
Bit 3
CPUSkw3
RW
0
Bit 2
CPUSkw2
RW
0
Bit 1
CPUSkw1
RW
0
Bit 0
CPUSkw0
RW
0
CPU Skew Programming Table
Byte 10 bits [7:4]
or bits [3:0]
Skew Value (ps)
0000
0
0001
100
0010
200
0011
300
0100
400
0101
500
0110
600
0111
700
1000
800
1001
900
1010
1000
1011
1100
1100
1200
1101
1300
1110
1400
1111
1500
290ms Base
CPUCLK0 Skew Control (ps)
Writing to this register will configure how
many bytes will be read back, default is
0F = 15 bytes.
Byte Count Programming
These bits represent X*290ms or X*1.16s.
The watchdog timer waits before it goes to
alarm mode. Default is 15 X 290ms =
4.35s.
CPUCLK1 Skew Control (ps)
See CPU Skew Programming Table
See CPU Skew Programming Table



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