ICS9LPRS436CKILF datasheet(8/20 Pages) IDT

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IDT®

Low Power Clock for Intel Atom®-Based Systems

1561A — 06/01/10

ICS9LPRS436C

Low Power Clock for Intel Atom

®-Based Systems

Electrical Characteristics - Absolute Maximum Ratings

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS NOTES

3.3V Core Supply Voltage

VDDA

4.6

1,2

3.3V Logic Supply Voltage

VDD

4.6

1,2

Input Low Voltage

VIL

GND-0.5

Input High Voltage

VIH

Except for SMBus interface

VDD+0.5V

Input High Voltage

VIHSMB

SMBus clock and data pins

5.5V

Storage Temperature

-65

150

°C

Case Temperature

Tcase

115

°C

Input ESD protection

ESD prot

Human Body Model

2000

1Guaranteed by design and characterization, not 100% tested in production.

2 Operation under these conditions is neither implied nor guaranteed.

Electrical Characteristics - Input/Supply/Common Output DC Parameters

PARAMETER

SYMBOL

CONDITIONS

MIN

TYP

MAX

UNITS

Notes

TambC

Standard Device

°C

TambI

Industrial Temperature Range Device

-40

°C

Supply Voltage

VDDxxx

Supply Voltage

3.135

3.465

Input High Voltage

VIHSE

Single-ended 3.3V inputs

VDD + 0.3

Input Low Voltage

VILSE

Single-ended 3.3V inputs

VSS - 0.3

0.8

FS(4:3) Input High Voltage

VIH_FS4

Single-ended 3.3V FS(4:3) Inputs

VDD + 0.3

FS(4:3) Input Low Voltage

VIL_FS4

Single-ended 3.3V FS(4:3) Inputs

VSS - 0.3

0.8

Low Threshold Input-

High Voltage

VIH_FS

3.3 V +/-5%

0.7

VDD+0.3

Low Threshold Input-

Low Voltage

VIL_FS

3.3 V +/-5%

VSS - 0.3

0.35

Input Leakage Current

IIN

VIN = VDD , VIN = GND

-5

Input Leakage Current

IINRES

Inputs with pull up or pull down resistors

VIN = VDD , VIN = GND

-200

200

Output High Voltage

VOHSE

Single-ended outputs, IOH = -1mA

2.4

Output Low Voltage

VOLSE

Single-ended outputs, IOL = 1 mA

0.4

IDDVDD3.3

Full Active, CL = Full load; IDD 3.3V

100

IDDVDDSUSP3.3

Full Active, CL = Full load; IDD 3.3V

IDDPDVDD3.3

3.3V Main Rail

IDDPDSUSP3.3w

VDD_SUSP Rail. 25MHz Running (WOL)

IDDPDSUSP3.3

VDD_SUSP Rail. 25MHz Off

Input Frequency

VDD = 3.3 V

MHz

Pin Inductance

Lpin

7nH

CIN

Logic Inputs

1.5

COUT

Output pin capacitance

CINX

X1 & X2 pins

SMBus Voltage

VDD

2.7

5.5

Low-level Output Voltage

VOLSMB

@ IPULLUP

0.4

Current sinking at

VOLSMB = 0.4 V

IPULLUP

SMB Data Pin

SCLK/SDATA

Clock/Data Rise Time

TRI2C

(Max VIL - 0.15) to

(Min VIH + 0.15)

1000

SCLK/SDATA

Clock/Data Fall Time

TFI2C

(Min VIH + 0.15) to

(Max VIL - 0.15)

300

Maximum SMBus Operating Frequency

FSMBUS

100

kHz

Spread Spectrum Modulation Frequency

fSSMOD

Triangular Modulation

kHz

1 Operation at these points is not recommended

4 Operation under these conditions is neither implied, nor guaranteed.

5Signal is required to be monotonic in this region.

6 Input leakage current does not include inputs with pull-up or pull-down resistors

2 Maximum VIH is not to exceed VDD

3 Human Body Model

8 For margining purposes only. Normal operation should have Fin = 25MHz +/-50ppm

7 3.3V referenced inputs are: PCI&PCIEX_STOP#, CPU_STOP#, ITP_EN, SCLK, SDATA, VTT_PWR_GD/PD#, SEL12_48# and PEREQ# inputs if selected.

NOTES on DC Parameters: (unless otherwise noted, guaranteed by design and characterization, not 100% tested in production).

Ambient Operating Temp

Operating Supply Current

Powerdown Current

Input Capacitance

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