LM3263

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SNVS837 – JUNE 2013

PCB LAYOUT CONSIDERATIONS

1. Overview

PC board layout is critical to successfully designing a DC-DC converter into a product. A properly planned board

layout optimizes the performance of a DC-DC converter and minimizes effects on surrounding circuitry while also

addressing manufacturing issues that can have adverse impacts on board quality and final product yield.

2. PCB

Poor board layout can disrupt the performance of a DC-DC converter and surrounding circuitry by contributing to

EMI, ground bounce, and resistive voltage loss in the traces. Erroneous signals could be sent to the DC-DC

converter IC, resulting in poor regulation or instability. Poor layout can also result in re-flow problems leading to

poor solder joints between the DSBGA package and board pads. Poor solder joints can result in erratic or

degraded performance of the converter.

Energy Efficiency

Minimize resistive losses by using wide traces between the power components and doubling up traces on

multiple layers when possible.

EMI

By its very nature, any switching converter generates electrical noise. The circuit board designer’s challenge is to

minimize, contain, or attenuate such switcher-generated noise. A high-frequency switching converter, such as the

LM3263, switches Ampere level currents within nanoseconds, and the traces interconnecting the associated

components can act as radiating antennas. The following guidelines are offered to help to ensure that EMI is

maintained within tolerable levels.

To help minimize radiated noise:

•

Place the LM3263 DC-DC converter, its input capacitor, and output filter inductor and capacitor close

together, and make the interconnecting traces as short as possible.

•

Arrange the components so that the switching current loops curl in the same direction. During the first half of

each cycle, current flows from the input filter capacitor, through the internal PFET of the LM3263 and the

inductor, to the output filter capacitor, then back through ground, forming a current loop. In the second half of

each cycle, current is pulled up from ground, through the internal synchronous NFET of the LM3263 by the

inductor, to the output filter capacitor and then back through ground, forming a second current loop. Routing

these loops so the current curls in the same direction prevents magnetic field reversal between the two half-

cycles and reduces radiated noise.

•

Make the current loop area(s) as small as possible. Interleave doubled traces with ground planes or return

paths, where possible, to further minimize trace inductances.

•

The Active Current Assist and Bypass (ACB) trace should be kept short and routed directly from ACB pads to

the VOUT pad at the inductor.

To help minimize conducted noise in the ground-plane:

•

Reduce the amount of switching current that circulates through the ground plane: Connect PGND bump of the

LM3263 and its input filter capacitor together using generous component-side copper fill as a pseudo-ground

plane. Then connect this copper fill to the system ground-plane (if one is used) by multiple vias located at the

input filter capacitor ground terminal. The multiple vias help to minimize ground bounce at the LM3263 by

giving it a low-impedance ground connection. Do not route the PGND pad directly to the RF ground plane.

•

An additional high frequency capacitor in 01005 (0402 mm) case size is also recommended between PVIN

and the RF ground plane. Do not connect to PGND directly.

•

For optimum RF performance connect the output capacitor ground to the RF ground or System ground plane.

Do not connect to PGND directly.

To help minimize coupling to the DC-DC converter's own voltage feedback trace:

•

Route noise sensitive traces, such as the voltage feedback path (FB), as directly as possible from the DC-DC

converter FB pad to the VOUT pad of the output capacitor, but keep it away from noisy traces between the

power components.

Copyright © 2013, Texas Instruments Incorporated

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