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STA381BW Datasheet(PDF) 55 Page - STMicroelectronics |
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STA381BW Datasheet(HTML) 55 Page - STMicroelectronics |
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55 / 174 page  DocID018835 Rev 8 55/174 STA381BW Register description: New Map For each configuration the PWM signals from the digital driver are mapped in different ways to the power stage. 2.0 channels, two full-bridges (OPER = 00) FFX1A -> OUT1A FFX1B -> OUT1B FFX2A -> OUT2A FFX2B -> OUT2B FFX3A -> OUT3A FFX3B -> OUT3B FFX4A -> OUT4A FFX4B -> OUT4B FFX1A/1B configured as ternary FFX2A/2B configured as ternary FFX3A/3B configured as line out ternary FFX4A/4B configured as line out ternary On channel 3 line out (LOC bits = 00, reg 0x17 bit D7,D6) the same data as channel 1 processing is sent. On channel 4 line out (LOC bits = 00) the same data as channel 2 processing is sent. In this configuration, neither volume control nor EQ has any effect on channels 3 and 4. In this configuration the PWM slot phase is the following as shown in Figure 23. Figure 23. 2.0 channels (OPER = 00) PWM slots OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B OUT1A OUT1B OUT2A OUT2B OUT3A OUT3B OUT4A OUT4B |
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