STA381BW datasheet(91/174 Pages) STMICROELECTRONICS

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STA381BW

Table 81. PLL register 0x54 bits

Bit

R/W

RST

Name

Description

R/W

PLL_DITH[1:0]

00: PLL clock dithering disabled

01: PLL clock dithering enabled (triangular)

10: PLL clock dithering enabled (rectangular)

11: reserved

R/W

PLL_NDIV

PLL loop divider

R/W

Table 82. PLL register 0x55 bits

Bit

R/W

RST

Name

Description

R/W

PLL_DPD

0: any PLL dividers change is implemented via PLL power-

down

1: PLL divider change will happen without PLL power-

down

R/W

PLL_FCT

0: PLL use integer ratio

1: PLL use fractional ratio

R/W

PLL_STB

PLL synchronous divider changes strobe

R/W

PLL_STBBYP

0: PLL_STB is active

1: PLL_STB control is bypassed

R/W

PLL_IDIV[3:0] Input PLL divider

R/W

Table 83. PLL register 0x56 bits

Bit

R/W

RST

Name

Description

R/W

PLL_DIRP

0: PLL configuration is determined by the MCS bits

1: PLL configuration is determined by FRAC, IDIV and NDIV

R/W

PLL_PWD

0: PLL normal behavior

1: PLL is in power-down mode

R/W

PLL_BYP

0: sys clock is from PLL

1: sys clock is from external pin (PLL is bypassed)

R/W

OSC_PD

0: Normal behavior

1: Internal oscillator is in power-down

R/W

BOOST32K

0: Input oversampling selected by the IR bits

1: Input oversampling is selected x3

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