JS28F256P30B95A datasheet(47/97 Pages) MICRON

47 / 97 page

August 2008

Datasheet

Order Number: 306666-12

P30

11.2.8

Burst Wrap

The Burst Wrap (BW) bit determines whether 4-word, 8-word, or 16-word burst length

accesses wrap within the selected word-length boundaries or cross word-length

boundaries. When BW is set, burst wrapping does not occur (default). When BW is

cleared, burst wrapping occurs.

When performing synchronous burst reads with BW set (no wrap), an output delay may

occur when the burst sequence crosses its first device-row (16-word) boundary. If the

burst sequence’s start address is 4-word aligned, then no delay occurs. If the start

address is at the end of a 4-word boundary, the worst case output delay is one clock

cycle less than the first access Latency Count. This delay can take place only once, and

doesn’t occur if the burst sequence does not cross a device-row boundary. WAIT

informs the system of this delay when it occurs.

11.2.9

Burst Length

The Burst Length bit (BL[2:0]) selects the linear burst length for all synchronous burst

reads of the flash memory array. The burst lengths are 4-word, 8-word, 16-word, and

continuous word.

Continuous-burst accesses are linear only, and do not wrap within any word length

boundaries (see Table 22, “Burst Sequence Word Ordering” on page 46). When a burst

cycle begins, the device outputs synchronous burst data until it reaches the end of the

“burstable” address space.

11.2.10

End of Word Line (EOWL) Considerations

When performing synchronous burst reads with BW set (no wrap) and DH reset (1 clock

cycle), an output “delay” requiring additions clock Wait States may occur when the

burst sequence crosses its first device-row (16-word) boundary. The delay would take

place only once, and will not occur if the burst sequence does not cross a device-row

boundary. The WAIT signal informs the system of this delay when it occurs. If the burst

sequence’s start address is 4-word aligned (i.e. 0x00h, 0x04h, 0x08h, 0x0Ch) then no

delay occurs. If the start address is at the end of a 4-word boundary (i.e. 0x03h,

0x07h, 0x0Bh, 0x0Fh), the worst case delay (number of Wait States required) will be

one clock cycle less than the first access Latency Count (LC-1) when crossing the first

device-row boundary (i.e. 0x0Fh to 0x10h). Other address misalignments may require

wait states depending upon the LC setting and the starting address alignment. For

example, an LC setting of 3 with a starting address of 0xFD requires 0 wait states, but

the same LC setting of 3 with a starting address of 0xFE would require 1 wait state

when crossing the first device row boundary.

11.3

One-Time-Programmable (OTP) Registers

The device contains 17 one-time-programmable (OTP) registers that can be used to

implement system security measures and/or device identification. Each OTP register

can be individually locked.

The first 128-bit OTP Register is comprised of two 64-bit (8-word) segments. The lower

64-bit segment is pre-programmed at the Numonyx factory with a unique 64-bit

number. The other 64-bit segment, as well as the other sixteen 128-bit OTP Registers,

are blank. Users can program these registers as needed. When programmed, users can

then lock the OTP Register(s) to prevent additional bit programming (see Figure 16,

“OTP register map” on page 48).

The OTP Registers contain one-time programmable (OTP) bits; when programmed, PR

bits cannot be erased. Each OTP Register can be accessed multiple times to program

individual bits, as long as the register remains unlocked.

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