JS28F512P30TFA datasheet(16/86 Pages) MICRON

16 / 86 page

P30-65nm

Datasheet

Sept 2012

Order Number: 208042-0

5.0

Bus Operations

CE# low and RST# high enable device read operations. The device internally decodes

upper address inputs to determine the accessed block. ADV# low opens the internal

address latches. OE# low activates the outputs and gates selected data onto the I/O

bus.

Bus cycles to/from the P30-65nm device conform to standard microprocessor bus

operations. Table 5, “Bus Operations Summary” summarizes the bus operations and

the logic levels that must be applied to the device control signal inputs.

5.1

Read - Asynchronous Single Word Mode

To perform an asynchronous single word read, an address is driven onto the address

bus, and CE# is asserted. ADV# must be held low throughout the read cycle for TSOP

package. ADV# can either be driven high to latch the address or be held low

throughout the read cycle for Easy BGA package. WE# and RST# must already have

been deasserted. WAIT is set to a deasserted state during single word mode as

determined by RCR.10. CLK is not used for asynchronous single word reads, and is

ignored. After OE# is asserted, the data is driven onto DQ[15:0] after an initial access

time tAVQV or tGLQV delay. (See Table 25, “AC Read Specifications -” on page 51).

Note:

If only asynchronous reads are to be performed, CLK should be tied to a valid

VIH level, WAIT signal can be floated and ADV# must be tied to ground.

Refer to the following waveforms for more detailed information. Figure 18,

“Asynchronous Single-Word Read (ADV# Low)” on page 52, and Figure 19,

“Asynchronous Single-Word Read for Easy BGA (ADV# Latch)” on page 53.

5.2

Read - Asynchronous Page Mode (Easy BGA)

To perform an asynchronous page read, an address is driven onto the address bus, and

CE# and ADV# are asserted. WE# and RST# must already have been deasserted.

WAIT is set to a deasserted state during asynchronous page mode and single word

mode as determined by RCR.10. ADV# can be driven high to latch the address, or it

must be held low throughout the read cycle. CLK is not used for asynchronous page-

mode reads, and is ignored. After OE# is asserted, the data is driven onto DQ[15:0]

after an initial access time tAVQV or tGLQV delay. (See Table 25, “AC Read Specifications

-” on page 51.)

Table 5:

Bus Operations Summary

Bus Operation

RST#

CLK

ADV#

CE#

OE#

WE#

WAIT

DQ[15:0]

Notes

Read

Asynchronous

VIH

Deasserted

Output

Synchronous

VIH

Running

Driven

Output

Write

VIH

High-Z

Input

Output Disable

VIH

High-Z

Standby

VIH

High-Z

Reset

VIL

High-Z

2,3

Notes:

Refer to the

Table 7, “Command Bus Cycles” on page 21 for valid DQ[15:0] during a write

operation.

X = Don’t Care (H or L).

RST# must be at VSS ± 0.2V to meet the maximum specified power-down current.

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