DSPIC33FJ12MC201TESS datasheet(28/304 Pages) MICROCHIP

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dsPIC33FJ12MC201/202

DS70265E-page 28

The SA and SB bits are modified each time data

passes through the adder/subtracter, but can only be

cleared by the user application. When set, they indicate

that the accumulator has overflowed its maximum

range (bit 31 for 32-bit saturation or bit 39 for 40-bit

saturation) and will be saturated (if saturation is

enabled). When saturation is not enabled, SA and SB

default to bit 39 overflow, and therefore, indicate that a

catastrophic overflow has occurred. If the COVTE bit in

the INTCON1 register is set, the SA and SB bits will

generate an arithmetic warning trap when saturation is

disabled.

The Overflow and Saturation Status bits can optionally

be viewed in the STATUS Register (SR) as the logical

OR of OA and OB (in bit OAB) and the logical OR of SA

and SB (in bit SAB). Programmers can check one bit in

the STATUS register to determine whether either

accumulator has overflowed, or one bit to determine

whether either accumulator has saturated. This is

useful for complex number arithmetic, which typically

uses both accumulators.

The device supports three Saturation and Overflow

modes:

• Bit 39 Overflow and Saturation:

When bit 39 overflow and saturation occurs, the

saturation logic loads the maximally positive 9.31

value (0x7FFFFFFFFF) or maximally negative 9.31

value (0x8000000000) into the target accumulator.

The SA or SB bit is set and remains set until

cleared by the user application. This condition is

referred to as ‘super saturation’ and provides pro-

tection against erroneous data or unexpected algo-

rithm problems (such as gain calculations).

• Bit 31 Overflow and Saturation:

When bit 31 overflow and saturation occurs, the

saturation logic then loads the maximally positive

1.31 value (0x007FFFFFFF) or maximally nega-

tive 1.31 value (0x0080000000) into the target

accumulator. The SA or SB bit is set and remains

set until cleared by the user application. When

this Saturation mode is in effect, the guard bits are

not used, so the OA, OB or OAB bits are never

set.

• Bit 39 Catastrophic Overflow:

The bit 39 Overflow Status bit from the adder is

used to set the SA or SB bit, which remains set

until cleared by the user application. No saturation

operation is performed, and the accumulator is

allowed to overflow, destroying its sign. If the

COVTE bit in the INTCON1 register is set, a

catastrophic overflow can initiate a trap exception.

3.6.3

ACCUMULATOR ‘WRITE BACK’

The MAC class of instructions (with the exception of

MPY, MPY.N, ED,

and EDAC) can optionally write a

rounded version of the high word (bits 31 through 16)

of the accumulator which is not targeted by the instruc-

tion into data space memory. The write is performed

across the X bus into combined X and Y address

space. The following addressing modes are supported:

• W13, Register Direct:

The rounded contents of the non-target

accumulator are written into W13 as a

1.15 fraction.

• [W13] + = 2, Register Indirect with Post-Increment:

The rounded contents of the non-target accumu-

lator are written into the address pointed to by

W13 as a 1.15 fraction. W13 is then incremented

by 2 (for a word write).

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