DSPIC33FJ12MC201TESS datasheet(288/304 Pages) MICROCHIP

288 / 304 page

dsPIC33FJ12MC201/202

DS70265E-page 288

Revision C (June 2008)

This revision includes minor typographical and

formatting changes throughout the data sheet text.

The major changes are referenced by their respective

section in the following table.

TABLE 25-1:

MAJOR SECTION UPDATES

Section Name

Update Description

“High-Performance, 16-bit

Digital Signal Controllers”

Added SSOP to list of available 28-pin packages (see “Packaging:” and

Table 1).

Added External Interrupts column to Remappable Peripherals in the Controller

Families table and Note 2 (see Table 1).

Added Note 1 to all pin diagrams, which references RPn pin usage by

remappable peripherals (see “Pin Diagrams”).

Section 1.0 “Device Overview”

Changed Capture Input pin names from IC0-IC1 to IC1-IC2 and updated

description for AVDD (see Table 1-1).

Section 3.0 “Memory

Organization”

Added SFR definitions (ACCAL, ACCAH, ACCAU, ACCBL, ACCBH, and

ACCBU) to the CPU Core Register Map (see Table 3-1).

Updated Reset values for the following SFRs: IPC0, IPC2-IPC7, IPC16, and

INTTREG (see Table 3-4).

Updated all SFR names in QEI1 Register Map (see Table 3-11).

The following changes were made to the ADC1 Register Maps:

• Updated the bit range for AD1CON3 from ADCS<5:0> to ADCS<7:0>)

(see Table 3-15 and Table 3-16).

• Added Bit 6 (PCFG7) and Bit 7 (PCFG6) names to AD1PCFGL (Table 3-15).

• Added Bit 6 (CSS7) and Bit 7 (CSS6) names to AD1CSSL (see Table 3-15).

• Changed Bit 5 and Bit 4 in AD1CSSL to unimplemented (see Table 3-15).

Updated the Reset value for CLKDIV in the System Control Register Map

(see Table 3-23).

Section 4.0 “Flash Program

Memory”

Updated Section 4.3 “Programming Operations” with programming time

formula.

Section 5.0 “Resets”

Entire section was replaced to maintain consistency with other dsPIC33F data

sheets.

Section 7.0 “Oscillator

Configuration”

Removed the first sentence of the third clock source item (External Clock) in

Section 7.1.1 “System Clock sources”

Updated the default bit values for DOZE and FRCDIV in the Clock Divisor

Added the center frequency in the OSCTUN register for the FRC Tuning bits

(TUN<5:0>) value 011111 and updated the center frequency for bits value

011110

(see Register 7-4)

Section 8.0 “Power-Saving

Features”

Added the following three registers:

• PMD1: Peripheral Module Disable Control Register 1

• PMD2: Peripheral Module Disable Control Register 2

• PMD3: Peripheral Module Disable Control Register 3

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