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DSPIC33FJ12MC201TESS Datasheet(PDF) 299 Page - Microchip Technology |
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DSPIC33FJ12MC201TESS Datasheet(HTML) 299 Page - Microchip Technology |
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299 / 304 page  © 2007-2011 Microchip Technology Inc. DS70265E-page 299 dsPIC33FJ12MC201/202 IPC3 (Interrupt Priority Control 3) ............................... 93 IPC4 (Interrupt Priority Control 4) ............................... 94 IPC5 (Interrupt Priority Control 5) ............................... 95 IPC7 (Interrupt Priority Control 7) ............................... 96 NVMCON (Flash Memory Control) ............................. 59 NVMKEY (Nonvolatile Memory Key) .......................... 60 OCxCON (Output Compare x Control) ..................... 154 OSCCON (Oscillator Control) ................................... 107 OSCTUN (FRC Oscillator Tuning) ............................ 111 P1DC3 (PWM Duty Cycle 3)..................................... 167 PLLFBD (PLL Feedback Divisor).............................. 110 PMD1 (Peripheral Module Disable Control Register 1) .. 115 PMD2 (Peripheral Module Disable Control Register 2) .. 116 PMD3 (Peripheral Module Disable Control Register 3) .. 117 PWMxCON1 (PWM Control 1).................................. 161 PWMxCON2 (PWM Control 2).................................. 162 PxDC1 (PWM Duty Cycle 1) ..................................... 167 PxDC2 (PWM Duty Cycle 2) ..................................... 167 PxDTCON1 (Dead-Time Control 1) .......................... 163 PxDTCON2 (Dead-Time Control 2) .......................... 164 PxFLTACON (Fault A Control).................................. 165 PxOVDCON (Override Control) ................................ 166 PxSECMP (Special Event Compare)........................ 160 PxTCON (PWM Time Base Control)......................... 158 PxTMR (PWM Timer Count Value)........................... 159 PxTPER (PWM Time Base Period) .......................... 159 QEICON (QEI Control).............................................. 170 RCON (Reset Control) ................................................ 64 SPIxCON1 (SPIx Control 1)...................................... 175 SPIxCON2 (SPIx Control 2)...................................... 177 SPIxSTAT (SPIx Status and Control) ....................... 174 SR (CPU Status)................................................... 22, 76 T1CON (Timer1 Control)........................................... 142 T2CON Control ......................................................... 146 T3CON Control ......................................................... 147 TCxCON (Input Capture x Control)........................... 150 UxMODE (UARTx Mode).......................................... 188 UxSTA (UARTx Status and Control)......................... 190 Reset Illegal Opcode ................................................. 63, 69, 70 Trap Conflict................................................................ 69 Uninitialized W Register.................................. 63, 69, 70 Reset Sequence ................................................................. 71 Resets................................................................................. 63 S Serial Peripheral Interface (SPI) ....................................... 173 Software Reset Instruction (SWR) ...................................... 69 Software Simulator (MPLAB SIM)..................................... 221 Software Stack Pointer, Frame Pointer CALLL Stack Frame.................................................... 48 Special Features of the CPU ............................................ 205 SPI Module SPI1 Register Map...................................................... 42 Symbols Used in Opcode Descriptions............................. 212 System Control Register Map............................................................... 47 T Temperature and Voltage Specifications AC ............................................................................. 234 Timer1............................................................................... 141 Timer2/3............................................................................ 143 Timing Characteristics CLKO and I/O ........................................................... 237 Timing Diagrams 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) ............................................. 268 10-bit A/D Conversion (CHPS<1:0> = 01, SIMSAM = 0, ASAM = 1, SSRC<2:0> = 111, SAMC<4:0> = 00001) .............................................................. 268 12-bit A/D Conversion (ASAM = 0, SSRC = 000)..... 267 Brown-out Situations .................................................. 68 External Clock .......................................................... 235 I2Cx Bus Data (Master Mode) .................................. 260 I2Cx Bus Data (Slave Mode) .................................... 262 I2Cx Bus Start/Stop Bits (Master Mode)................... 260 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 262 Input Capture (CAPx) ............................................... 242 Motor Control PWM .................................................. 244 Motor Control PWM Fault ......................................... 244 OC/PWM .................................................................. 243 Output Compare (OCx) ............................................ 243 QEA/QEB Input ........................................................ 245 QEI Module Index Pulse........................................... 246 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer ................................................ 238 Timer1, 2 and 3 External Clock ................................ 240 TimerQ (QEI Module) External Clock ....................... 242 Timing Requirements CLKO and I/O ........................................................... 237 DCI AC-Link Mode.................................................... 264 DCI Multi-Channel, I2S Modes ................................. 264 External Clock .......................................................... 235 Input Capture............................................................ 243 Timing Specifications 10-bit A/D Conversion Requirements ....................... 269 12-bit A/D Conversion Requirements ....................... 267 I2Cx Bus Data Requirements (Master Mode)........... 261 I2Cx Bus Data Requirements (Slave Mode)............. 263 Motor Control PWM Requirements........................... 245 Output Compare Requirements................................ 243 PLL Clock ................................................................. 236 QEI External Clock Requirements............................ 242 QEI Index Pulse Requirements ................................ 247 Quadrature Decoder Requirements ......................... 246 Reset, Watchdog Timer, Oscillator Start-up Timer, Pow- er-up Timer and Brown-out Reset Requirements... 239 Simple OC/PWM Mode Requirements ..................... 244 Timer1 External Clock Requirements....................... 240 Timer2 External Clock Requirements....................... 241 Timer3 External Clock Requirements....................... 241 U UART Module UART1 Register Map ................................................. 42 Universal Asynchronous Receiver Transmitter (UART) ... 187 Using the RCON Status Bits............................................... 70 V Voltage Regulator (On-Chip) ............................................ 208 W Watchdog Time-out Reset (WDTR).................................... 69 Watchdog Timer (WDT)............................................ 205, 209 Programming Considerations ................................... 209 WWW Address ................................................................. 301 WWW, On-Line Support ....................................................... 8 |
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