DSPIC33FJ12MC202TESS datasheet(70/304 Pages) MICROCHIP

70 / 304 page

dsPIC33FJ12MC201/202

DS70265E-page 70

6.9.1

ILLEGAL OPCODE RESET

A device Reset is generated if the device attempts to

execute an illegal opcode value that is fetched from

program memory.

The illegal opcode Reset function can prevent the

device from executing program memory sections that

are used to store constant data. To take advantage of

the illegal opcode Reset, use only the lower 16 bits of

each program memory section to store the data values.

The upper 8 bits should be programmed with 3Fh,

which is an illegal opcode value.

6.9.2

UNINITIALIZED W REGISTER

RESET

Any attempts to use the uninitialized W register as an

address pointer will Reset the device. The W register

array (with the exception of W15) is cleared during all

Resets and is considered uninitialized until written to.

6.9.3

SECURITY RESET

If a Program Flow Change (PFC) or Vector Flow

Change (VFC) targets a restricted location in a

protected segment (Boot and Secure Segment), that

operation will cause a security Reset.

The PFC occurs when the Program Counter is

reloaded as a result of a Call, Jump, Computed Jump,

Return, Return from Subroutine, or other form of

branch instruction.

The VFC occurs when the Program Counter is

reloaded with an Interrupt or Trap vector.

Refer to Section 21.8 “Code Protection and

CodeGuard™ Security”

for more information on

Security Reset.

6.10

Using the RCON Status Bits

The user application can read the Reset Control

(RCON) register after any device Reset to determine

the cause of the Reset.

Table 6-3 provides a summary of Reset flag bit

operation.

TABLE 6-3:

RESET FLAG BIT OPERATION

Note:

The status bits in the RCON register

should be cleared after they are read so

that the next RCON register value after a

device Reset will be meaningful.

Flag Bit

Set by:

Cleared by:

TRAPR (RCON<15>)

Trap conflict event

POR, BOR

IOPWR (RCON<14>)

Illegal opcode or uninitialized

W register access or Security Reset

POR, BOR

CM (RCON<9>)

Configuration Mismatch

POR, BOR

EXTR (RCON<7>)

MCLR Reset

POR

SWR (RCON<6>)

RESET

instruction

POR, BOR

WDTO (RCON<4>)

WDT Time-out

PWRSAV

instruction,

CLRWDT

instruction, POR, BOR

SLEEP (RCON<3>)

PWRSAV #SLEEP

instruction

POR, BOR

IDLE (RCON<2>)

PWRSAV #IDLE

instruction

POR, BOR

BOR (RCON<1>)

POR, BOR

—

POR (RCON<0>)

POR

—

Note:

All Reset flag bits can be set or cleared by user software.

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