PIC16F1825T-ESS datasheet(247/448 Pages) MICROCHIP

247 / 448 page

 2010-2012 Microchip Technology Inc.

DS41440C-page 247

PIC16(L)F1825/1829

25.2.3

SPI MASTER MODE

The master can initiate the data transfer at any time

because it controls the SCKx line. The master

determines when the slave (Processor 2, Figure 25-5)

is to broadcast data by the software protocol.

In Master mode, the data is transmitted/received as

soon as the SSPxBUF register is written to. If the SPI

is only going to receive, the SDOx output could be

disabled (programmed as an input). The SSPxSR

SDIx pin at the programmed clock rate. As each byte is

received, it will be loaded into the SSPxBUF register as

if a normal received byte (interrupts and Status bits

appropriately set).

The clock polarity is selected by appropriately

programming the CKP bit of the SSPxCON1 register

and the CKE bit of the SSPxSTAT register. This then,

would give waveforms for SPI communication as

shown in Figure 25-6, Figure 25-8, Figure 25-9 and

Figure 25-10, where the MSB is transmitted first. In

Master mode, the SPI clock rate (bit rate) is user

programmable to be one of the following:

•FOSC/4 (or TCY)

•FOSC/16 (or 4 * TCY)

•FOSC/64 (or 16 * TCY)

• Timer2 output/2

•FOSC/(4 * (SSPxADD + 1))

Figure 25-6 shows the waveforms for Master mode.

When the CKE bit is set, the SDOx data is valid before

there is a clock edge on SCKx. The change of the input

sample is shown based on the state of the SMP bit. The

time when the SSPxBUF is loaded with the received

data is shown.

FIGURE 25-6:

SPI MODE WAVEFORM (MASTER MODE)

SCKx

(CKP = 0

SCKx

(CKP = 1

SCKx

(CKP = 0

SCKx

(CKP = 1

4 Clock

Modes

Input

Sample

Input

Sample

SDIx

bit 7

bit 0

SDOx

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

bit 7

SDIx

SSPxIF

(SMP = 1)

(SMP = 0)

(SMP = 1)

CKE = 1)

CKE = 0)

CKE = 1)

CKE = 0)

(SMP = 0)

Write to

SSPxBUF

SSPxSR to

SSPxBUF

SDOx

bit 7

bit 6

bit 5

bit 4

bit 3

bit 2

bit 1

bit 0

(CKE = 0)

(CKE = 1)

bit 0

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