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DSPIC33FJ32MC302EMM Datasheet(PDF) 110 Page - Microchip Technology |
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DSPIC33FJ32MC302EMM Datasheet(HTML) 110 Page - Microchip Technology |
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110 / 460 page ![]() dsPIC33FJ32MC302/304, dsPIC33FJ64MCX02/X04 AND dsPIC33FJ128MCX02/X04 DS70291G-page 110 © 2007-2012 Microchip Technology Inc. REGISTER 7-13: IEC3: INTERRUPT ENABLE CONTROL REGISTER 3 R/W-0 R/W-0 R/W-0 U-0 U-0 R/W-0 R/W-0 U-0 FLTA1IE RTCIE DMA5IE — —QEI1IE PWM1IE — bit 15 bit 8 U-0 U-0 U-0 U-0 U-0 U-0 U-0 U-0 — — — — — — — — bit 7 bit 0 Legend: R = Readable bit W = Writable bit U = Unimplemented bit, read as ‘0’ -n = Value at POR ‘1’ = Bit is set ‘0’ = Bit is cleared x = Bit is unknown bit 15 FLTA1IE: PWM1 Fault A Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 14 RTCIE: Real-Time Clock and Calendar Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 13 DMA5IE: DMA Channel 5 Data Transfer Complete Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 12-11 Unimplemented: Read as ‘0’ bit 10 QEI1IE: QEI1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 9 PWM1IE: PWM1 Event Interrupt Enable bit 1 = Interrupt request enabled 0 = Interrupt request not enabled bit 8-0 Unimplemented: Read as ‘0’ |
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