IMX53IEC datasheet(26/173 Pages) FREESCALE

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i.MX53 Applications Processors for Industrial Products, Rev. 6

Freescale Semiconductor

Electrical Characteristics

4.2.2

Power-Down Sequence

Power-down sequence should follow one of the following two options:

•

Option 1: Switch all supplies down simultaneously with further free discharge. A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

•

Option 2: Switch down supplies, in any order, keeping the following rules:

— NVCC_CKIH must be powered down at the same time or after the UHVIO I/O cell supplies

(for full supply list, see Table 6, Ultra High voltage I/O (UHVIO) supplies). A deviation of few

microseconds of actual power-down of the different power rails is acceptable.

— VDD_REG must be powered down at the same time or after NVCC_EMI_DRAM supply. A

deviation of few microseconds of actual power-down of the different power rails is acceptable.

— If all of the following conditions are met:

– VDD_REG is powered down to 0V (Not Hi-Z)

– VDD_DIG_PLL and VDD_ANA_PLL are provided externally,

– VDD_REG is powered down before VDD_DIG_PLL and VDD_ANA_PLL

Then the following rule should be kept: VDD_REG output impedance must be higher than 1

kW, when inactive.

4.2.3

Power Supplies Usage

•

All I/O pins should not be externally driven while the I/O power supply for the pin (NVCC_xxx)

is off. This can cause internal latch-up and malfunctions due to reverse current flows. For

information about I/O power supply of each pin, see “Power Rail” columns in pin list tables of

Section 6, “Package Information and Contact Assignments.”

•

If not using SATA interface and the embedded thermal sensor, the VP and VPH should be

grounded. In particular, keeping VPH turned OFF while the VP is powered ON is not

recommended and might lead to excessive power consumption.

•

When internal clock source is used for SATA temperature monitor the USB_PHY supplies and

PLL need to be active because they are providing the clock.

•

If not using the TVE module, the TVDAC_DHVDD and TVDAC_AHVDDRGB can be kept

floating or tied to GND—the recommendation is to float. If only the GPIO pads in

TVDAC_AHVDDRGB domain are in use, the supplies can be set to GPIO pad voltage range

(1.65V to 3.1V).

4.3

I/O DC Parameters

This section includes the DC parameters of the following I/O types:

•

General Purpose I/O (GPIO)

•

Double Data Rate 3 I/O (DDR3) for DDR2/LVDDR2, LPDDR2 and DDR3 modes

•

Low Voltage I/O (LVIO)

•

Ultra High Voltage I/O (UHVIO)

•

LVDS I/O

IMX53IEC Datasheet(PDF) 26 Page - Freescale Semiconductor, Inc

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