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FDC37C78-HT Datasheet(PDF) 79 Page - Microchip Technology |
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FDC37C78-HT Datasheet(HTML) 79 Page - Microchip Technology |
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79 / 82 page  79 t3 t1 t2 t4 t5 t6 t7 t8 t9 t9 nDIR nSTEP nDS0-1 nINDEX nRDATA nWDATA nIOW nDS0-1, nMTR0-1 FIGURE 7 - DISK DRIVE TIMING *X specifies one MCLK period and Y specifies one WCLK period. MCLK = Controller Clock to FDC (See Table 6). WCLK = 2 x Data Rate (See Table 6). Parameter min typ max units t1 t2 t3 t4 t5 t6 t7 t8 t9 nDIR Set Up to nSTEP Low nSTEP Active Time Low nDIR Hold Time After nSTEP nSTEP Cycle Time nDS0-1 Hold Time from nSTEP Low nINDEX Pulse Width nRDATA Active Time Low nWDATA Write Data Width Low nDS0-1, MTR0-1 from End of nIOW X* X* X* X* X* X* ns Y* ns 4 24 96 132 20 2 40 .5 25 |
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