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LPC81XM Datasheet(PDF) 52 Page - NXP Semiconductors

Part # LPC81XM
Description  32-bit ARM Cortex-M0 microcontroller; up to 16 kB flash and 4 kB SRAM
PDF  71 Pages
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Manufacturer  NXP [NXP Semiconductors]
Direct Link  http://www.nxp.com
Logo NXP - NXP Semiconductors

LPC81XM Datasheet(HTML) 52 Page - NXP Semiconductors

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LPC81xM
All information provided in this document is subject to legal disclaimers.
© NXP B.V. 2013. All rights reserved.
Product data sheet
Rev. 3 — 29 July 2013
52 of 71
NXP Semiconductors
LPC81xM
32-bit ARM Cortex-M0+ microcontroller
12.7 USART interface
The maximum USART bit rate is 1.875 Mbit/s in asynchronous mode and 10 Mbit/s in
synchronous mode slave and master mode.
Remark: USART functions can be assigned to all digital pins. The characteristics are valid
for all digital pins except the open-drain pins PIO0_10 and PIO0_11.
[1]
Typical ratings are not guaranteed. The values listed are for room temperature (25
C), V
DD = 3.3 V, typical
samples.
[2]
Tcy(clk) = U_PCLK/BRGVAL. See the LPC800 User manual UM10601.
[3]
Capacitance on pin Un_SCLK CSCLK < 5 pF.
Table 18.
USART dynamic characteristics
Tamb = 40 C to 105 C; 1.8 V <= VDD <= 3.6 V. Simulated parameters sampled at the 50 % level of
the falling or rising edge; values guaranteed by design.
Symbol
Parameter
Conditions
Min
Max
Unit
Tcy(clk)
clock cycle time
[2]
100
-
ns
USART master (in synchronous mode)[3]
tsu(D)
data input set-up
time
44
-
ns
th(D)
data input hold time
0
-
ns
tv(Q)
data output valid time
-
-8
ns
th(Q)
data output hold time
-8
-
ns
USART slave (in synchronous mode)
tsu(D)
data input set-up
time
5-
ns
th(D)
data input hold time
0
-
ns
tv(Q)
data output valid time CL = 10 pF
-
40
ns
th(Q)
data output hold time CL = 10 pF
40
-
ns
Fig 32. USART timing



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