PIC18F1220ESLASHSSSQTP datasheet(30/308 Pages) MICROCHIP

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PIC18F1220/1320

DS39605F-page 28

3.4.4

EXIT TO IDLE MODE

An exit from a power managed Run mode to its

corresponding Idle mode is executed by setting the

IDLEN bit and executing a SLEEP instruction. The CPU

is halted at the beginning of the instruction following the

SLEEP

instruction. There are no changes to any of the

clock source status bits (OSTS, IOFS or T1RUN).

While the CPU is halted, the peripherals continue to be

clocked from the previously selected clock source.

3.4.5

EXIT TO SLEEP MODE

An exit from a power managed Run mode to Sleep

mode is executed by clearing the IDLEN and

SCS1:SCS0 bits and executing a SLEEP instruction.

The code is no different than the method used to invoke

Sleep mode from the normal operating (full power)

mode.

The primary clock and internal oscillator block are

disabled. The INTRC will continue to operate if the

WDT is enabled. The Timer1 oscillator will continue to

run, if enabled in the T1CON register (Register 12-1).

All clock source status bits are cleared (OSTS, IOFS

and T1RUN).

3.5

Wake from Power Managed Modes

An exit from any of the power managed modes is trig-

gered by an interrupt, a Reset or a WDT time-out. This

section discusses the triggers that cause exits from

power managed modes. The clocking subsystem

actions are discussed in each of the power managed

modes (see Sections 3.2 through 3.4).

Device behavior during Low-Power mode exits is

summarized in Table 3-3.

3.5.1

EXIT BY INTERRUPT

Any of the available interrupt sources can cause the

device to exit a power managed mode and resume full

power operation. To enable this functionality, an inter-

rupt source must be enabled by setting its enable bit in

one of the INTCON or PIE registers. The exit sequence

is initiated when the corresponding interrupt flag bit is

set. On all exits from Low-Power mode by interrupt,

code execution branches to the interrupt vector if the

GIE/GIEH bit (INTCON<7>) is set. Otherwise, code

execution continues or resumes without branching

(see Section 9.0 “Interrupts”).

Note:

If application code is timing sensitive, it

should wait for the OSTS bit to become set

before continuing. Use the interval during

the low-power exit sequence (before

OSTS is set) to perform timing insensitive

“housekeeping” tasks.

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