PIC18F1220ESLASHSSSQTP datasheet(303/308 Pages) MICROCHIP

303 / 308 page

DS39605F-page 301

PIC18F1220/1320

Time-out Sequence on POR w/PLL Enabled

(MCLR Tied to VDD) ........................................... 40

Time-out Sequence on Power-up

(MCLR Not Tied to Vdd), Case 1 ....................... 39

Time-out Sequence on Power-up

(MCLR Not Tied to Vdd), Case 2 ....................... 39

Time-out Sequence on Power-up

(MCLR Tied to Vdd, Vdd Rise pwrt) ................... 39

Timer0 and Timer1 External Clock .......................... 261

Transition for Entry to SEC_IDLE Mode .................... 24

Transition for Entry to SEC_RUN Mode .................... 26

Transition for Entry to Sleep Mode ............................ 22

Transition for Two-Speed Start-up

(INTOSC to HSPLL) ......................................... 181

Transition for Wake from PRI_IDLE Mode ................. 23

Transition for Wake from RC_RUN Mode

(RC_RUN to PRI_RUN) ..................................... 25

Transition for Wake from SEC_RUN Mode

(HSPLL) ............................................................. 24

Transition for Wake from Sleep (HSPLL) ................... 22

Transition to PRI_IDLE Mode .................................... 23

Transition to RC_IDLE Mode ..................................... 25

Transition to RC_RUN Mode ..................................... 27

Timing Diagrams and Specifications ................................ 257

Capture/Compare/PWM Requirements

(All CCP Modules) ........................................... 263

CLKO and I/O Requirements ................................... 259

EUSART Synchronous Receive Requirements ....... 264

EUSART Synchronous

Transmission Requirements ............................ 263

External Clock Requirements .................................. 257

Internal RC Accuracy ............................................... 258

PLL Clock, HS/HSPLL Mode

(VDD = 4.2V to 5.5V) ........................................ 258

Reset, Watchdog Timer, Oscillator

Start-up Timer, Power-up Timer and

Brown-out Reset Requirements ....................... 261

Timer0 and Timer1 External Clock

Requirements ................................................... 262

Top-of-Stack Access .......................................................... 42

TSTFSZ ........................................................................... 231

Two-Speed Start-up ..................................................171, 181

Two-Word Instructions ....................................................... 46

Example Cases .......................................................... 46

TXSTA Register

BRGH Bit ................................................................. 135

Watchdog Timer (WDT) ............................................171, 180

Associated Registers ............................................... 181

Control Register ....................................................... 180

During Oscillator Failure .......................................... 182

Programming Considerations .................................. 180

WWW Address ................................................................ 302

WWW, On-Line Support ...................................................... 4

XORLW ............................................................................ 231

XORWF ........................................................................... 232

PIC18F1220E/SSSQTP Datasheet(PDF) 303 Page - Microchip Technology

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