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PIC18F1220E/SSSQTP Datasheet(PDF) 106 Page - Microchip Technology

Part # PIC18F1220E/SSSQTP
Description  18/20/28-Pin High-Performance, Enhanced Flash Microcontrollers
PDF  308 Pages
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Manufacturer  MICROCHIP [Microchip Technology]
Direct Link  http://www.microchip.com
Logo MICROCHIP - Microchip Technology

PIC18F1220E/SSSQTP Datasheet(HTML) 106 Page - Microchip Technology

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PIC18F1220/1320
DS39605F-page 104
© 2007 Microchip Technology Inc.
12.1
Timer1 Operation
Timer1 can operate in one of these modes:
•As a timer
• As a synchronous counter
• As an asynchronous counter
The operating mode is determined by the clock select
bit, TMR1CS (T1CON<1>).
When TMR1CS = 0, Timer1 increments every instruc-
tion cycle. When TMR1CS = 1, Timer1 increments on
every rising edge of the external clock input, or the
Timer1 oscillator, if enabled.
When the Timer1 oscillator is enabled (T1OSCEN is
set), the RB7/PGD/T1OSI/P1D/KBI3 and RB6/T1OSO/
T13CKI/P1C/KBI2 pins become inputs. That is, the
TRISB7:TRISB6 values are ignored and the pins read
as ‘0’.
Timer1 also has an internal “Reset input”. This Reset
can
be
generated
by
the
CCP
module
(see
Section 15.4.4 “Special Event Trigger”).
FIGURE 12-1:
TIMER1 BLOCK DIAGRAM
FIGURE 12-2:
TIMER1 BLOCK DIAGRAM: 16-BIT READ/WRITE MODE
TMR1H
TMR1L
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Peripheral Clocks
FOSC/4
Internal
Clock
TMR1ON
On/Off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
TMR1IF
Overflow
TMR1
CLR
CCP Special Event Trigger
T1OSCEN
Enable
Oscillator(1)
T1OSC
Interrupt
Flag bit
Note 1:
When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates
power drain.
T1OSI
T13CKI/T1OSO
Timer 1
TMR1L
T1OSC
T1SYNC
TMR1CS
T1CKPS1:T1CKPS0
Peripheral Clocks
T1OSCEN
Enable
Oscillator(1)
TMR1IF
Overflow
Interrupt
FOSC/4
Internal
Clock
TMR1ON
on/off
Prescaler
1, 2, 4, 8
Synchronize
det
1
0
0
1
Synchronized
Clock Input
2
T13CKI/T1OSO
T1OSI
TMR1
Flag bit
Note 1:
When enable bit, T1OSCEN, is cleared, the inverter and feedback resistor are turned off. This eliminates power drain.
High Byte
Data Bus<7:0>
8
TMR1H
8
8
8
Read TMR1L
Write TMR1L
CLR
CCP Special Event Trigger



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