PIC18F1220ESLASHSSSQTP datasheet(137/308 Pages) MICROCHIP

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DS39605F-page 135

PIC18F1220/1320

16.2

EUSART Baud Rate Generator

(BRG)

The BRG is a dedicated 8-bit or 16-bit generator, that

supports both the Asynchronous and Synchronous

modes of the EUSART. By default, the BRG operates

in 8-bit mode; setting the BRG16 bit (BAUDCTL<3>)

selects 16-bit mode.

The SPBRGH:SPBRG register pair controls the period

of a free running timer. In Asynchronous mode, bits

BRGH (TXSTA<2>) and BRG16 also control the baud

rate. In Synchronous mode, bit BRGH is ignored.

Table 16-1 shows the formula for computation of the

baud rate for different EUSART modes which only

apply in Master mode (internally generated clock).

Given the desired baud rate and FOSC, the nearest

integer value for the SPBRGH:SPBRG registers can be

calculated using the formulas in Table 16-1. From this,

the error in baud rate can be determined. An example

calculation is shown in Example 16-1. Typical baud

rates and error values for the various asynchronous

modes

are

shown

Table 16-2.

may

advantageous to use the high baud rate (BRGH = 1),

or the 16-bit BRG to reduce the baud rate error, or

achieve a slow baud rate for a fast oscillator frequency.

Writing a new value to the SPBRGH:SPBRG registers

causes the BRG timer to be reset (or cleared). This

ensures the BRG does not wait for a timer overflow

before outputting the new baud rate.

16.2.1

POWER MANAGED MODE

OPERATION

The system clock is used to generate the desired baud

rate; however, when a power managed mode is

entered, the clock source may be operating at a differ-

ent frequency than in PRI_RUN mode. In Sleep mode,

no clocks are present and in PRI_IDLE mode, the

primary clock source continues to provide clocks to the

Baud Rate Generator; however, in other power

managed modes, the clock frequency will probably

change. This may require the value in SPBRG to be

adjusted.

If the system clock is changed during an active receive

operation, a receive error or data loss may result. To

avoid this problem, check the status of the RCIDL bit

and make sure that the receive operation is Idle before

changing the system clock.

16.2.2

SAMPLING

The data on the RB4/AN6/RX/DT/KBI0 pin is sampled

three times by a majority detect circuit to determine if a

high or a low level is present at the RX pin.

TABLE 16-1:

BAUD RATE FORMULAS

EXAMPLE 16-1:

CALCULATING BAUD RATE ERROR

Configuration Bits

BRG/EUSART Mode

Baud Rate Formula

SYNC

BRG16

BRGH

8-bit/Asynchronous

FOSC/[64 (n + 1)]

8-bit/Asynchronous

FOSC/[16 (n + 1)]

16-bit/Asynchronous

FOSC/[4 (n + 1)]

8-bit/Synchronous

16-bit/Synchronous

Legend: x = Don’t care, n = value of SPBRGH:SPBRG register pair

For a device with FOSC of 16 MHz, desired baud rate of 9600, Asynchronous mode, 8-bit BRG:

Desired Baud Rate =

FOSC/(64 ([SPBRGH:SPBRG] + 1))

Solving for SPBRGH:SPBRG:

((FOSC/Desired Baud Rate)/64) – 1

((16000000/9600)/64) – 1

[25.042] = 25

Calculated Baud Rate =

16000000/(64 (25 + 1))

9615

Error

(Calculated Baud Rate – Desired Baud Rate)/Desired Baud Rate

(9615 – 9600)/9600 = 0.16%

PIC18F1220E/SSSQTP Datasheet(PDF) 137 Page - Microchip Technology

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