PIC18F1220ESLASHSSSQTP datasheet(187/308 Pages) MICROCHIP

187 / 308 page

DS39605F-page 185

PIC18F1220/1320

19.5

Program Verification and

Code Protection

The overall structure of the code protection on the

PIC18 Flash devices differs significantly from other PIC

devices.

The user program memory is divided into three blocks.

One of these is a boot block of 512 bytes. The remain-

der of the memory is divided into two blocks on binary

boundaries.

Each of the three blocks has three protection bits

associated with them. They are:

• Code-Protect bit (CPn)

• Write-Protect bit (WRTn)

• External Block Table Read bit (EBTRn)

Figure 19-5 shows the program memory organization

for 4 and 8-Kbyte devices and the specific code protec-

tion bit associated with each block. The actual locations

of the bits are summarized in Table 19-3.

FIGURE 19-5:

CODE-PROTECTED PROGRAM MEMORY FOR PIC18F1220/1320

TABLE 19-3:

SUMMARY OF CODE PROTECTION REGISTERS

Block Code

Protection

Controlled By:

MEMORY SIZE/DEVICE

Block Code

Protection

Controlled By:

Address

Range

4Kbytes

(PIC18F1220)

8Kbytes

(PIC18F1320)

Address

Range

CPB, WRTB, EBTRB

000000h

0001FFh

Boot Block

000000h

0001FFh

CPB, WRTB, EBTRB

CP0, WRT0, EBTR0

000200h

0007FFh

Block 0

000200h

CP0, WRT0, EBTR0

CP1, WRT1, EBTR1

000800h

000FFFh

Block 1

000FFFh

(Unimplemented

Memory Space)

001000h

Unimplemented

Read ‘0’s

Block 1

001000h

CP1, WRT1, EBTR1

001FFFh

1FFFFFh

Unimplemented

Read ‘0’s

002000h

1FFFFFh

(Unimplemented

Memory Space)

File Name

Bit 7

Bit 6

Bit 5

Bit 4

Bit 3

Bit 2

Bit 1

Bit 0

300008h

CONFIG5L

—

—CP1

CP0

300009h

CONFIG5H

CPD

CPB

—

30000Ah

CONFIG6L

—

WRT1

WRT0

30000Bh

CONFIG6H

WRTD

WRTB

WRTC

—

30000Ch

CONFIG7L

—

EBTR1

EBTR0

30000Dh

CONFIG7H

—

EBTRB

—

Legend: Shaded cells are unimplemented.

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