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AD9920ABBCZ Datasheet(PDF) 28 Page - Analog Devices |
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AD9920ABBCZ Datasheet(HTML) 28 Page - Analog Devices |
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28 / 112 page ![]() AD9920A Rev. B | Page 28 of 112 PHASE 1 PHASE 3 PHASE 2 H1/H2 H5/H6 H7/H8 MASK LEVEL = HIGH MASK LEVEL = HIGH MASK LEVEL = LOW BLANKING A3 A2 A B B3 B2 B1 A1 1 PIXEL 1 PIXEL 1 PIXEL 1 PIXEL 1 PIXEL INTERNAL DIGITAL CLOCK MASTER BLANKING SIGNAL Figure 34. Incorrect HBLK Behavior Caused by Internal Clock Position PHASE 1 PHASE 3 PHASE 2 INTERNAL DIGITAL CLOCK MASTER BLANKING SIGNAL H1/H2 H5/H6 H7/H8 1 PIXEL 1 PIXEL 1 PIXEL 1 PIXEL 1 PIXEL A3 A2 A1 A B B3 B2 B1 FINE RETIME FINE RETIME FINE RETIME FINE RETIME MASK LEVEL = HIGH MASK LEVEL = HIGH MASK LEVEL = LOW BLANKING Figure 35. Fine Retime on Phase 2 to Achieve Correct HBLK |
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