ADS8344EB datasheet(14/25 Pages) TI

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ADS8344

SBAS139E

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tACQ

Acquisition Time

1.5

µs

tDS

DIN Valid Prior to DCLK Rising

100

tDH

DIN Hold After DCLK HIGH

tDO

DCLK Falling to DOUT Valid

200

tDV

CS Falling to DOUT Enabled

200

tTR

CS Rising to DOUT Disabled

200

tCSS

CS Falling to First DCLK Rising

100

tCSH

CS Rising to DCLK Ignored

tCH

DCLK HIGH

200

tCL

DCLK LOW

200

tBD

DCLK Falling to BUSY Rising

200

tBDV

CS Falling to BUSY Enabled

200

tBTR

CS Rising to BUSY Disabled

200

TABLE VI. Timing Specifications (+VCC = +2.7V to 3.6V,

TA = –40°C to +85°C, CLOAD = 50pF).

Since one clock cycle of the serial clock is consumed with

BUSY going HIGH (while the MSB decision is being

made), 16 additional clocks must be given to clock out all 16

bits of data; thus, one conversion takes a minimum of 25

clock cycles to fully read the data. Since most microproces-

sors communicate in 8-bit transfers, this means that an

additional transfer must be made to capture the LSB.

There are two ways of handling this requirement. One is

where the beginning of the next control byte appears at the

same time the LSB is being clocked out of the ADS8344

(see Figure 3). This method allows for maximum throughput

and 24 clock cycles per conversion.

The other method is shown in Figure 5, which uses 32 clock

cycles per conversion; the last seven clock cycles simply

shift out zeros on the DOUT line. BUSY and DOUT go into a

high-impedance state when CS goes HIGH; after the next

CS falling edge, BUSY will go LOW.

Internal Clock Mode

In internal clock mode, the ADS8344 generates its own

conversion clock internally. This relieves the microproces-

sor from having to generate the SAR conversion clock and

allows the conversion result to be read back at the processor’s

convenience, at any clock rate from 0MHz to 2.0MHz.

BUSY goes LOW at the start of a conversion and then

returns HIGH when the conversion is complete. During the

conversion, BUSY will remain LOW for a maximum of 8

µs.

Also, during the conversion, DCLK should remain LOW to

achieve the best noise performance. The conversion result is

stored in an internal register; the data may be clocked out of

this register any time after the conversion is complete.

ACQ

Acquire

Idle

Conversion

DCLK

DOUT

BUSY

(MSB)

(START)

(LSB)

DIN

SGL/

DIF

PD1 PD0

7654321

Idle

Zero Filled...

If CS is LOW when BUSY goes LOW following a conver-

sion, the next falling edge of the external serial clock will

write out the MSB on the DOUT line. The remaining bits

(D14-D0) will be clocked out on each successive clock cycle

following the MSB. If CS is HIGH when BUSY goes LOW

then the DOUT line will remain in tri-state until CS goes

LOW, as shown in Figure 6. CS does not need to remain

LOW once a conversion has started. Note that BUSY is not

tri-stated when CS goes HIGH in internal clock mode.

Data can be shifted in and out of the ADS8344 at clock rates

exceeding 2.4MHz, provided that the minimum acquisition

time tACQ, is kept above 1.7µs.

Digital Timing

Figure 4 and Tables VI and VII provide detailed timing for

the digital interface of the ADS8344.

ACQ

Acquire

Idle

Conversion

DCLK

1011

2021

2829

DOUT

BUSY

(MSB)

(START)

(LSB)

DIN

SGL/

DIF

PD1 PD0

7654321

Zero Filled...

FIGURE 5. External Clock Mode, 32 Clocks Per Conversion.

FIGURE 6. Internal Clock Mode Timing.

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