ADS8344EB datasheet(15/25 Pages) TI

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ADS8344

SBAS139E

SYMBOL

DESCRIPTION

MIN

TYP

MAX

UNITS

tACQ

Acquisition Time

1.7

µs

tDS

DIN Valid Prior to DCLK Rising

tDH

DIN Hold After DCLK HIGH

tDO

DCLK Falling to DOUT Valid

100

tDV

CS Falling to DOUT Enabled

tTR

CS Rising to DOUT Disabled

tCSS

CS Falling to First DCLK Rising

tCSH

CS Rising to DCLK Ignored

tCH

DCLK HIGH

150

tCL

DCLK LOW

150

tBD

DCLK Falling to BUSY Rising

100

tBDV

CS Falling to BUSY Enabled

tBTR

CS Rising to BUSY Disabled

FIGURE 7. Ideal Input Voltages and Output Codes.

TABLE VII. Timing Specifications (+VCC = +4.75V to

+5.25V, TA = –40°C to +85°C, CLOAD = 50pF).

FS = Full-Scale Voltage = V

REF

1LSB = V

REF/65,536

FS – 1LSB

11...111

11...110

11...101

00...010

00...001

00...000

1LSB

NOTE: (1) Voltage at converter input, after multiplexer: +IN – (–IN). (See Figure 2.)

Input Voltage(1) (V)

Data Format

The ADS8344 output data is in straight binary format, as

shown in Figure 7. This figure shows the ideal output code

for the given input voltage and does not include the effects

of offset, gain, or noise.

POWER DISSIPATION

There are three power modes for the ADS8344: full-power

(PD1 - PD0 = 11B), auto power-down (PD1 - PD0 = 00B),

and shutdown (SHDN LOW). The effects of these modes

varies depending on how the ADS8344 is being operated.

For example, at full conversion rate and 24-clocks per

conversion, there is very little difference between

full-power mode and auto power-down; a shutdown will not

lower power dissipation.

When operating at full-speed and 24-clocks per conversion

(see Figure 3), the ADS8344 spends most of its time

acquiring or converting. There is little time for auto

power-down, assuming that this mode is active. Thus, the

difference between full-power mode and auto power-down

is negligible. If the conversion rate is decreased by simply

slowing the frequency of the DCLK input, the two modes

remain approximately equal. However, if the DCLK fre-

quency is kept at the maximum rate during a conversion, but

conversions are simply done less often, then the difference

between the two modes is dramatic. In the latter case, the

converter spends an increasing percentage of its time in

power-down mode (assuming the auto power-down mode is

active).

If DCLK is active and CS is LOW while the ADS8344 is in

auto power-down mode, the device will continue to dissipate

some power in the digital logic. The power can be reduced

to a minimum by keeping CS HIGH.

Operating the ADS8344 in auto power-down mode will

result in the lowest power dissipation, and there is no

conversion time “penalty” on power-up. The very first

conversion will be valid. SHDN can be used to force an

immediate power-down.

NOISE

The noise floor of the ADS8344 itself is extremely low, as

shown in Figures 8 thru 11, and is much lower than compet-

ing A/D converters. The ADS8344 was tested at both 5V

and 2.7V, and in both the internal and external clock modes.

A low-level DC input was applied to the analog-input pins

and the converter was put through 5,000 conversions. The

digital output of the A/D converter will vary in output code

due to the internal noise of the ADS8344. This is true for all

16-bit SAR-type A/D converters. Using a histogram to plot

the output codes, the distribution should appear bell-shaped

with the peak of the bell curve representing the nominal code

for the input value. The

±1σ, ±2σ, and ±3σ distributions will

represent the 68.3%, 95.5%, and 99.7%, respectively, of all

codes. The transition noise can be calculated by dividing the

number of codes measured by 6 and this will yield the

±3σ

distribution, or 99.7%, of all codes. Statistically, up to 3

codes could fall outside the distribution when executing

1,000 conversions. The ADS8344, with < 3 output codes for

the

±3σ distribution, will yield a < ±0.5LSB transition noise

at 5V operation. Remember, to achieve this low-noise per-

formance, the peak-to-peak noise of the input signal and

reference must be < 50

µV.

FIGURE 8. Histogram of 5,000 Conversions of a DC Input at the

Code Transition, 5V operation external clock mode.

Code

4561

242

197

7FFE

7FFD

8001

8000

7FFF

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