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DSPIC33FJ12GP201TE/ML Datasheet(PDF) 236 Page - Microchip Technology |
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DSPIC33FJ12GP201TE/ML Datasheet(HTML) 236 Page - Microchip Technology |
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236 / 242 page  dsPIC33FJ12GP201/202 DS70264B-page 234 Preliminary © 2007 Microchip Technology Inc. I I/O Ports .............................................................................. 99 Parallel I/O (PIO)......................................................... 99 Write/Read Timing .................................................... 100 I2C Addresses ................................................................. 145 Baud Rate Generator................................................ 143 General Call Address Support .................................. 145 Interrupts................................................................... 143 IPMI Support ............................................................. 145 Master Mode Operation Clock Arbitration................................................ 146 Multi-Master Communication, Bus Collision and Bus Arbitration ................................... 146 Operating Modes ...................................................... 143 Registers................................................................... 143 Slave Address Masking ............................................ 145 Slope Control ............................................................ 146 Software Controlled Clock Stretching (STREN = 1).. 145 I2C Module I2C1 Register Map ...................................................... 32 In-Circuit Debugger ........................................................... 178 In-Circuit Emulation........................................................... 173 In-Circuit Serial Programming (ICSP) ....................... 173, 178 Infrared Support Built-in IrDA Encoder and Decoder........................... 155 External IrDA, IrDA Clock Output.............................. 155 Input Capture Registers................................................................... 128 Input Change Notification.................................................. 100 Instruction Addressing Modes............................................. 38 File Register Instructions ............................................ 38 Fundamental Modes Supported.................................. 39 MAC Instructions......................................................... 39 MCU Instructions ........................................................ 38 Move and Accumulator Instructions ............................ 39 Other Instructions........................................................ 39 Instruction Set Overview ................................................................... 182 Summary................................................................... 179 Instruction-Based Power-Saving Modes ............................. 97 Idle .............................................................................. 98 Sleep........................................................................... 97 Internal RC Oscillator Use with WDT ........................................................... 177 Internet Address................................................................ 237 Interrupt Control and Status Registers................................ 63 IECx ............................................................................ 63 IFSx............................................................................. 63 INTCON1 .................................................................... 63 INTCON2 .................................................................... 63 IPCx ............................................................................ 63 Interrupt Setup Procedures ................................................. 85 Initialization ................................................................. 85 Interrupt Disable.......................................................... 85 Interrupt Service Routine ............................................ 85 Trap Service Routine .................................................. 85 Interrupt Vector Table (IVT) ................................................ 59 Interrupts Coincident with Power Save Instructions............ 98 J JTAG Boundary Scan Interface ........................................ 173 M Memory Organization ......................................................... 23 Microchip Internet Web Site.............................................. 237 Modulo Addressing ............................................................. 40 Applicability................................................................. 41 Operation Example ..................................................... 40 Start and End Address ............................................... 40 W Address Register Selection .................................... 40 MPLAB ASM30 Assembler, Linker, Librarian ................... 188 MPLAB ICD 2 In-Circuit Debugger ................................... 189 MPLAB ICE 2000 High-Performance Universal In-Circuit Emulator.................................................... 189 MPLAB Integrated Development Environment Software.. 187 MPLAB PM3 Device Programmer .................................... 189 MPLAB REAL ICE In-Circuit Emulator System ................ 189 MPLINK Object Linker/MPLIB Object Librarian ................ 188 N NVM Module Register Map .............................................................. 37 O Open-Drain Configuration................................................. 100 Output Compare ............................................................... 129 Registers .................................................................. 133 P Packaging ......................................................................... 225 Details....................................................................... 226 Marking..................................................................... 225 Peripheral Module Disable (PMD) ...................................... 98 Peripheral Pin Select Input Register Map ..................................................... 33 PICSTART Plus Development Programmer..................... 190 Pinout I/O Descriptions (table).............................................. 9 PMD Module Register Map .............................................................. 37 POR and Long Oscillator Start-up Times ........................... 57 PORTA Register Map .............................................................. 36 PORTB Register Map .............................................................. 36 Power-Saving Features ...................................................... 97 Clock Frequency and Switching ................................. 97 Program Address Space..................................................... 23 Construction ............................................................... 43 Data Access from Program Memory Using Program Space Visibility..................................... 46 Data Access from Program Memory Using Table Instructions ......................................................... 45 Data Access from, Address Generation ..................... 44 Memory Map............................................................... 23 Table Read Instructions TBLRDH ............................................................. 45 TBLRDL.............................................................. 45 Visibility Operation...................................................... 46 Program Memory Interrupt Vector ........................................................... 24 Organization ............................................................... 24 Reset Vector............................................................... 24 Pulse-Width Modulation Mode.......................................... 130 PWM Duty Cycle ................................................................ 130 Period ....................................................................... 130 |
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