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DSPIC33FJ12GP201TE/ML Datasheet(PDF) 237 Page - Microchip Technology |
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DSPIC33FJ12GP201TE/ML Datasheet(HTML) 237 Page - Microchip Technology |
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237 / 242 page  © 2007 Microchip Technology Inc. Preliminary DS70264B-page 235 dsPIC33FJ12GP201/202 R Reader Response ............................................................. 238 Registers AD1CHS0 (ADC1 Input Channel 0 Select ................ 170 AD1CHS123 (ADC1 Input Channel 1, 2, 3 Select) ... 168 AD1CON1 (ADC1 Control 1) .................................... 164 AD1CON2 (ADC1 Control 2) .................................... 166 AD1CON3 (ADC1 Control 3) .................................... 167 AD1CSSL (ADC1 Input Scan Select Low)................ 171 AD1PCFGL (ADC1 Port Configuration Low) ............ 171 CLKDIV (Clock Divisor)............................................... 92 CORCON (Core Control) ...................................... 16, 64 I2CxCON (I2Cx Control) ........................................... 147 I2CxMSK (I2Cx Slave Mode Address Mask) ............ 151 I2CxSTAT (I2Cx Status) ........................................... 149 ICxCON (Input Capture x Control) ............................ 128 IEC0 (Interrupt Enable Control 0) ............................... 72 IEC1 (Interrupt Enable Control 0) ............................... 74 IEC4 (Interrupt Enable Control 0) ............................... 75 IFS0 (Interrupt Flag Status 0) ..................................... 68 IFS1 (Interrupt Flag Status 1) ..................................... 70 IFS4 (Interrupt Flag Status 4) ..................................... 71 INTCON1 (Interrupt Control 1).................................... 65 INTCON2 (Interrupt Control 2).................................... 67 INTTREG Interrupt Control and Status Register......... 84 IPC0 (Interrupt Priority Control 0) ............................... 76 IPC1 (Interrupt Priority Control 1) ............................... 77 IPC16 (Interrupt Priority Control 16) ........................... 83 IPC2 (Interrupt Priority Control 2) ............................... 78 IPC3 (Interrupt Priority Control 3) ............................... 79 IPC4 (Interrupt Priority Control 4) ............................... 80 IPC5 (Interrupt Priority Control 5) ............................... 81 IPC7 (Interrupt Priority Control 7) ............................... 82 NVMCON (Flash Memory Control) ............................. 49 NVMCON (Nonvolatile Memory Key).......................... 50 OCxCON (Output Compare x Control) ..................... 133 OSCCON (Oscillator Control) ..................................... 90 OSCTUN (FRC Oscillator Tuning) .............................. 94 PLLFBD (PLL Feedback Divisor)................................ 93 RCON (Reset Control) ................................................ 54 SPIxCON1 (SPIx Control 1)...................................... 140 SPIxCON2 (SPIx Control 2)...................................... 142 SPIxSTAT (SPIx Status and Control) ....................... 139 SR (CPU Status)................................................... 14, 64 T1CON (Timer1 Control)........................................... 120 T2CON Control ......................................................... 124 T3CON Control ......................................................... 125 UxMODE (UARTx Mode).......................................... 156 UxSTA (UARTx Status and Control)......................... 158 Reset Clock Source Selection............................................... 56 Special Function Register Reset States ..................... 57 Times .......................................................................... 56 Reset Sequence ................................................................. 59 Resets................................................................................. 53 S Serial Peripheral Interface (SPI) ....................................... 135 Setup for Continuous Output Pulse Generation ............... 129 Setup for Single Output Pulse Generation........................ 129 Software Simulator (MPLAB SIM) .................................... 188 Software Stack Pointer, Frame Pointer CALL Stack Frame ..................................................... 38 Special Features of the CPU ............................................ 173 SPI Master, Frame Master Connection ........................... 137 Master/Slave Connection ......................................... 137 Slave, Frame Master Connection ............................. 138 Slave, Frame Slave Connection ............................... 138 SPI Module SPI1 Register Map ..................................................... 32 Symbols Used in Opcode Descriptions ............................ 180 System Control Register Map .............................................................. 36 T Temperature and Voltage Specifications AC............................................................................. 200 Timer1 .............................................................................. 119 Timer2/3 ........................................................................... 121 Timing Characteristics CLKO and I/O ........................................................... 203 Timing Diagrams 10-bit A/D Conversion .............................................. 223 10-bit A/D Conversion (CHPS = 01, SIMSAM = 0, ASAM = 0, SSRC = 000) .................................. 223 12-bit A/D Conversion (ASAM = 0, SSRC = 000)..... 222 External Clock .......................................................... 201 I2Cx Bus Data (Master Mode) .................................. 215 I2Cx Bus Data (Slave Mode) .................................... 217 I2Cx Bus Start/Stop Bits (Master Mode)................... 215 I2Cx Bus Start/Stop Bits (Slave Mode)..................... 217 Input Capture (CAPx) ............................................... 208 OC/PWM .................................................................. 209 Output Compare (OCx) ............................................ 208 Reset, Watchdog Timer, Oscillator Start-up Timer and Power-up Timer............................... 204 SPIx Master Mode (CKE = 0) ................................... 210 SPIx Master Mode (CKE = 1) ................................... 211 SPIx Slave Mode (CKE = 0) ..................................... 212 SPIx Slave Mode (CKE = 1) ..................................... 213 Timer1, 2 and 3 External Clock ................................ 206 Timing Requirements CLKO and I/O ........................................................... 203 DCI AC-Link Mode.................................................... 219 DCI Multi-Channel, I2S Modes ................................. 219 External Clock .......................................................... 201 Input Capture............................................................ 208 Timing Specifications 10-bit A/D Conversion Requirements ....................... 224 12-bit A/D Conversion Requirements ....................... 222 I2Cx Bus Data Requirements (Master Mode)........... 216 I2Cx Bus Data Requirements (Slave Mode)............. 218 Output Compare Requirements................................ 208 PLL Clock ................................................................. 202 Reset, Watchdog Timer, Oscillator Start-up Timer, Power-up Timer and Brown-out Reset Requirements ................................................... 205 Simple OC/PWM Mode Requirements ..................... 209 SPIx Master Mode (CKE = 0) Requirements............ 210 SPIx Master Mode (CKE = 1) Requirements............ 211 |
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