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DSPIC30F2011AT-30E/PF Datasheet(PDF) 203 Page - Microchip Technology |
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DSPIC30F2011AT-30E/PF Datasheet(HTML) 203 Page - Microchip Technology |
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203 / 228 page ![]() © 2006 Microchip Technology Inc. DS70117F-page 201 dsPIC30F6011/6012/6013/6014 FIGURE 23-18: I2C™ BUS START/STOP BITS TIMING CHARACTERISTICS (MASTER MODE) FIGURE 23-19: I2C™ BUS DATA TIMING CHARACTERISTICS (MASTER MODE) SP50 TssL2scH, TssL2scL SSX ↓ to SCKX↓ or SCKX↑ input 120 — — ns — SP51 TssH2doZ SS ↑ to SDOX Output Hi-Impedance(4) 10 — 50 ns — SP52 TscH2ssH TscL2ssH SSX ↑ after SCKX Edge 1.5 TCY + 40 — — ns — SP60 TssL2doV SDOX Data Output Valid after SSX Edge —— 50 ns — TABLE 23-34: SPI MODULE SLAVE MODE (CKE = 1) TIMING REQUIREMENTS (CONTINUED) AC CHARACTERISTICS Standard Operating Conditions: 2.5V to 5.5V (unless otherwise stated) Operating temperature -40°C ≤ TA ≤ +85°C for Industrial -40°C ≤ TA ≤ +125°C for Extended Param No. Symbol Characteristic(1) Min Typ(2) Max Units Conditions Note 1: These parameters are characterized but not tested in manufacturing. 2: Data in “Typ” column is at 5V, 25°C unless otherwise stated. Parameters are for design guidance only and are not tested. 3: The minimum clock period for SCK is 100 ns. Therefore, the clock generated in master mode must not violate this specification. 4: Assumes 50 pF load on all SPI pins. IM31 IM34 SCL SDA Start Condition Stop Condition IM30 IM33 Note: Refer to Figure 23-3 for load conditions. IM11 IM10 IM33 IM11 IM10 IM20 IM26 IM25 IM40 IM40 IM45 IM21 SCL SDA In SDA Out Note: Refer to Figure 23-3 for load conditions. |
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