DSPIC30F2011AT-30ESLASHPF datasheet(50/228 Pages) MICROCHIP

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dsPIC30F6011/6012/6013/6014

DS70117F-page 48

Execution of a “BRA #literal” instruction or a

“GOTO #literal” instruction, where literal

is an unimplemented program memory address.

Executing instructions after modifying the PC to

point

unimplemented

program

memory

addresses. The PC may be modified by loading

a value into the stack and executing a RETURN

instruction.

Stack Error Trap:

This trap is initiated under the following conditions:

The Stack Pointer is loaded with a value which

is greater than the (user programmable) limit

value written into the SPLIM register (stack

overflow).

The Stack Pointer is loaded with a value which

is less than 0x0800 (simple stack underflow).

Oscillator Fail Trap:

This trap is initiated if the external oscillator fails and

operation becomes reliant on an internal RC backup.

5.3.2

HARD AND SOFT TRAPS

It is possible that multiple traps can become active

within the same cycle (e.g., a misaligned word stack

write to an overflowed address). In such a case, the

fixed priority shown in Figure 5-1 is implemented,

which may require the user to check if other traps are

pending in order to completely correct the fault.

‘Soft’ traps include exceptions of priority level 8 through

level 11, inclusive. The arithmetic error trap (level 11)

falls into this category of traps.

‘Hard’ traps include exceptions of priority level 12

through level 15, inclusive. The address error (level

12), stack error (level 13) and oscillator error (level 14)

traps fall into this category.

Each hard trap that occurs must be Acknowledged

before code execution of any type may continue. If a

lower priority hard trap occurs while a higher priority

trap is pending, Acknowledged, or is being processed,

a hard trap conflict will occur.

The device is automatically reset in a hard trap conflict

condition. The TRAPR status bit (RCON<15>) is set

when the Reset occurs so that the condition may be

detected in software.

FIGURE 5-1:

TRAP VECTORS

5.4

Interrupt Sequence

All interrupt event flags are sampled in the beginning of

each instruction cycle by the IFSx registers. A pending

interrupt request (IRQ) is indicated by the flag bit being

equal to a ‘1’ in an IFSx register. The IRQ will cause an

interrupt to occur if the corresponding bit in the Interrupt

Enable (IECx) register is set. For the remainder of the

instruction cycle, the priorities of all pending interrupt

requests are evaluated.

If there is a pending IRQ with a priority level greater

than the current processor priority level in the IPL bits,

the processor will be interrupted.

The processor then stacks the current program counter

and the low byte of the processor STATUS register

(SRL), as shown in Figure 5-2. The low byte of the

STATUS register contains the processor priority level at

the time prior to the beginning of the interrupt cycle.

The processor then loads the priority level for this inter-

rupt into the STATUS register. This action will disable

all lower priority interrupts until the completion of the

Interrupt Service Routine.

Address Error Trap Vector

Oscillator Fail Trap Vector

Stack Error Trap Vector

Reserved Vector

Math Error Trap Vector

Reserved

Oscillator Fail Trap Vector

Address Error Trap Vector

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

Interrupt 52 Vector

Interrupt 53 Vector

Math Error Trap Vector

0x000000

0x000014

Reserved

Stack Error Trap Vector

Reserved Vector

Interrupt 0 Vector

Interrupt 1 Vector

Interrupt 52 Vector

Interrupt 53 Vector

IVT

AIVT

0x000080

0x00007E

0x0000FE

Reserved

0x000094

Reset - GOTO Instruction

Reset - GOTO Address

0x000002

Reserved

0x000082

0x000084

0x000004

Reserved Vector

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