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DSPIC30F2011AT-30E/PF Datasheet(PDF) 66 Page - Microchip Technology |
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DSPIC30F2011AT-30E/PF Datasheet(HTML) 66 Page - Microchip Technology |
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66 / 228 page ![]() dsPIC30F6011/6012/6013/6014 DS70117F-page 64 © 2006 Microchip Technology Inc. 8.2 Configuring Analog Port Pins The use of the ADPCFG and TRIS registers control the operation of the A/D port pins. The port pins that are desired as analog inputs must have their correspond- ing TRIS bit set (input). If the TRIS bit is cleared (out- put), the digital output level (VOH or VOL) will be converted. When reading the Port register, all pins configured as analog input channels will read as cleared (a low level). Pins configured as digital inputs will not convert an ana- log input. Analog levels on any pin that is defined as a digital input (including the ANx pins) may cause the input buffer to consume current that exceeds the device specifications. FIGURE 8-2: BLOCK DIAGRAM OF A SHARED PORT STRUCTURE Q D CK WR LAT + TRIS Latch I/O Pad WR Port Data Bus Q D CK Data Latch Read LAT Read Port Read TRIS 1 0 1 0 WR TRIS Peripheral Output Data Output Enable Peripheral Input Data I/O Cell Peripheral Module Peripheral Output Enable PIO Module Output Multiplexers Output Data Input Data Peripheral Module Enable |
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