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DSPIC30F2011AT-30E/PF Datasheet(PDF) 222 Page - Microchip Technology |
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DSPIC30F2011AT-30E/PF Datasheet(HTML) 222 Page - Microchip Technology |
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222 / 228 page ![]() dsPIC30F6011A/6012A/6013A/6014A DS70143C-page 220 © 2006 Microchip Technology Inc. O OC/PWM Module Timing Characteristics.......................... 192 Operating Current (IDD)..................................................... 175 Oscillator Configurations ........................................................... 148 Fail-Safe Clock Monitor..................................... 149 Fast RC (FRC) .................................................. 149 Initial Clock Source Selection ........................... 148 Low Power RC (LPRC) ..................................... 149 LP Oscillator Control ......................................... 148 Phase Locked Loop (PLL) ................................ 149 Start-up Timer (OST) ........................................ 148 Operating Modes (Table) .......................................... 146 System Overview ...................................................... 145 Oscillator Selection ........................................................... 145 Oscillator Start-up Timer Timing Characteristics .............................................. 187 Timing Requirements ................................................ 187 Output Compare Interrupts ................................................. 89 Output Compare Module ..................................................... 87 Register Map............................................................... 90 Timing Characteristics .............................................. 191 Timing Requirements ................................................ 191 Output Compare Operation During CPU Idle Mode ............ 89 Output Compare Sleep Mode Operation............................. 89 P Packaging Information ...................................................... 211 Marking ..................................................................... 211 Peripheral Module Disable (PMD) Registers .................... 158 PICSTART Plus Development Programmer ..................... 172 Pinout Descriptions ............................................................. 12 PLL Clock Timing Specifications....................................... 184 POR. See Power-on Reset. PORTA Register Map for dsPIC30F6013/6014 ....................... 65 PORTB Register Map for dsPIC30F6011/6012/6013/6014 ..... 65 PORTC Register Map for dsPIC30F6011/6012 ....................... 65 Register Map for dsPIC30F6013/6014 ....................... 65 PORTD Register Map for dsPIC30F6011/6012 ....................... 66 Register Map for dsPIC30F6013/6014 ....................... 66 PORTF Register Map for dsPIC30F6011/6012 ....................... 66 Register Map for dsPIC30F6013/6014 ....................... 66 PORTG Register Map for dsPIC30F6011/6012/6013/6014 ..... 66 Power Saving Modes ........................................................ 156 Idle ............................................................................ 157 Sleep ......................................................................... 156 Sleep and Idle ........................................................... 145 Power-Down Current (IPD) ................................................ 177 Power-up Timer Timing Characteristics .............................................. 187 Timing Requirements ................................................ 187 Program Address Space..................................................... 25 Construction ............................................................... 27 Data Access from Program Memory Using Program Space Visibility .......................... 29 Data Access from Program Memory Using Table Instructions ............................................... 28 Data Access from, Address Generation ..................... 27 Data Space Window into Operation............................ 30 Data Table Access (LS Word) .................................... 28 Data Table Access (MS Byte)..................................... 29 Memory Map for dsPIC30F6011/6013........................ 26 Memory Map for dsPIC30F6012/6014........................ 26 Table Instructions TBLRDH ............................................................. 28 TBLRDL .............................................................. 28 TBLWTH ............................................................. 28 TBLWTL ............................................................. 28 Program and EEPROM Characteristics............................ 181 Program Counter ................................................................ 16 Programmable .................................................................. 145 Programmer’s Model .......................................................... 16 Diagram ...................................................................... 17 Programming Operations.................................................... 53 Algorithm for Program Flash....................................... 53 Erasing a Row of Program Memory............................ 53 Initiating the Programming Sequence......................... 54 Loading Write Latches ................................................ 54 Protection Against Accidental Writes to OSCCON ........... 150 R Reader Response............................................................. 224 Reset ........................................................................ 145, 151 BOR, Programmable ................................................ 153 Brown-out Reset (BOR)............................................ 145 Oscillator Start-up Timer (OST) ................................ 145 POR Operating without FSCM and PWRT................ 153 With Long Crystal Start-up Time ...................... 153 POR (Power-on Reset)............................................. 151 Power-on Reset (POR)............................................. 145 Power-up Timer (PWRT) .......................................... 145 Reset Sequence ................................................................. 47 Reset Sources ............................................................ 47 Reset Sources Brown-out Reset (BOR).............................................. 47 Illegal Instruction Trap ................................................ 47 Trap Lockout............................................................... 47 Uninitialized W Register Trap ..................................... 47 Watchdog Time-out .................................................... 47 Reset Timing Characteristics............................................ 187 Reset Timing Requirements ............................................. 187 RTSP Operation ................................................................. 52 Run-Time Self-Programming (RTSP) ................................. 51 |
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