DSPIC30F2011AT-30ESLASHS datasheet(139/238 Pages) MICROCHIP

139 / 238 page

Preliminary

DS70143C-page 137

dsPIC30F6011A/6012A/6013A/6014A

The following figure depicts the recommended circuit

for the conversion rates above 100 ksps. The

dsPIC30F6014A is shown as an example.

FIGURE 19-2:

ADC VOLTAGE REFERENCE SCHEMATIC

The configuration procedures below give the required

setup values for the conversion speeds above 100

ksps.

19.7.1

200 KSPS CONFIGURATION

GUIDELINE

The following configuration items are required to

achieve a 200 ksps conversion rate.

• Comply with conditions provided in Table 19-2.

• Connect external VREF+ and VREF- pins following

the recommended circuit shown in Figure 19-2.

• Set SSRC<2.0> = 111 in the ADCON1 register to

enable the auto convert option.

• Enable automatic sampling by setting the ASAM

control bit in the ADCON1 register.

• Write the SMPI<3.0> control bits in the ADCON2

between interrupts.

• Configure the ADC clock period to be:

by writing to the ADCS<5:0> control bits in the

ADCON3 register.

• Configure the sampling time to be 1 TAD by

writing: SAMC<4:0> = 00001.

The following figure shows the timing diagram of the

ADC running at 200 ksps. The TAD selection in con-

junction with the guidelines described above allows a

conversion speed of 200 ksps. See Example 19-1 for

code example.

VSS

VDD

VSS

dsPIC30F6014A

VDD

0.1

μF

0.01

μF

VDD

0.1

μF

VDD

0.01

μF

AVDD

μF

AVDD

0.1

μF

AVDD

0.01

μF

See Note 1:

Note 1: Ensure adequate bypass capacitors are provided on each VDD pin.

(14 + 1) x 200,000

= 334 ns

DSPIC30F2011AT-30E/S Datasheet(PDF) 139 Page - Microchip Technology

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